Datasheet

AD5662
Rev. A | Page 5 of 24
TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2. See Figure 2.
V
DD
= 2.7 V to 5.5 V; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Limit at T
MIN
, T
MAX
Parameter V
DD
= 2.7 V to 3.6 V V
DD
= 3.6 V to 5.5 V Unit Conditions/Comments
t
1
1
50 33 ns min SCLK cycle time
t
2
13 13 ns min SCLK high time
t
3
13 13 ns min SCLK low time
t
4
13 13 ns min
SYNC
to SCLK falling edge setup time
t
5
5 5 ns min Data setup time
t
6
4.5 4.5 ns min Data hold time
t
7
0 0 ns min
SCLK falling edge to SYNC
rising edge
t
8
50 33 ns min
Minimum SYNC
high time
t
9
13 13 ns min
SYNC
rising edge to SCLK fall ignore
t
10
0 0 ns min
SCLK falling edge to SYNC
fall ignore
1
Maximum SCLK frequency is 30 MHz at V
DD
= 3.6 V to 5.5 V, and 20 MHz at V
DD
= 2.7 V to 3.6 V.
DIN
SYNC
SCLK
DB23
DB0
t
9
t
10
t
4
t
3
t
2
t
7
t
6
t
5
t
1
t
8
04777-002
Figure 2. Serial Write Operation