Datasheet

AD5662
Rev. A | Page 14 of 24
THEORY OF OPERATION
DAC SECTION
The AD5662 DAC is fabricated on a CMOS process. The
architecture consists of a string DAC followed by an output
buffer amplifier. Figure 32 shows a block diagram of the DAC
architecture.
V
DD
R
R
V
OUT
GND
RESISTOR
STRING
REF (+)
REF (–)

OUTPUT
AMPLIFIER
DAC REGISTER
04777-022
V
FB
Figure 32. DAC Architecture
Since the input coding to the DAC is straight binary, the ideal
output voltage is given by
⎟
⎠
⎞
⎜
⎝
⎛
×=
65,536
D
VV
REF
OUT
where D is the decimal equivalent of the binary code that is
loaded to the DAC register. It can range from 0 to 65,535.
RESISTOR STRING
The resistor string section is shown in Figure 33. It is simply a
string of resistors, each of value R. The code loaded to the DAC
register determines at which node on the string the voltage is
tapped off to be fed into the output amplifier. The voltage is
tapped off by closing one of the switches connecting the string
to the amplifier. Because it is a string of resistors, it is guaranteed
monotonic.
R
R
R
R
R
TO OUTPUT
AMPLIFIER
04777-023
Figure 33. Resistor String
OUTPUT AMPLIFIER
The output buffer amplifier can generate rail-to-rail voltages on
its output, which gives an output range of 0 V to V
DD
. This output
buffer amplifier has a gain of 2 derived from a 50 kΩ resistor
divider network in the feedback path. The output amplifier’s
inverting input is available to the user, allowing for remote
sensing. This V
FB
pin must be connected to V
OUT
for normal
operation. It can drive a load of 2 kΩ in parallel with 1000 pF to
GND. The source and sink capabilities of the output amplifier can
be seen in Figure 15. The slew rate is 1.5 V/μs with a ¼ to ¾
full-scale settling time of 10 μs.
SERIAL INTERFACE
The AD5662 has a 3-wire serial interface (
SYNC
, SCLK, and
DIN) that is compatible with SPI, QSPI, and MICROWIRE
interface standards as well as with most DSPs. See for
a timing diagram of a typical write sequence.
Figure 2
The write sequence begins by bringing the
SYNC
line low. Data
from the DIN line is clocked into the 24-bit shift register on the
falling edge of SCLK. The serial clock frequency can be as high
as 30 MHz, making the AD5662 compatible with high speed
DSPs. On the 24
th
falling clock edge, the last data bit is clocked
in and the programmed function is executed, that is, a change
in DAC register contents and/or a change in the mode of opera-
tion. At this stage, the
SYNC
line can be kept low or be brought
high. In either case, it must be brought high for a minimum of
33 ns before the next write sequence so that a falling edge of
SYNC
can initiate the next write sequence. Since the
SYNC
buffer draws more current when V
IN
= 2.4 V than it does when
V
IN
= 0.8 V,
SYNC
should be idled low between write sequences
for even lower power operation. As mentioned previously it
must, however, be brought high again just before the next write
sequence.