Datasheet

AD5628/AD5648/AD5668 Data Sheet
Rev. G | Page 24 of 32
INTERNAL REFERENCE REGISTER
The on-board reference is off at power-up by default. This allows
the use of an external reference if the application requires it. The
on-board reference can be turned on or off by a user-program-
mable internal REF register by setting Bit DB0 high or low (see
Table 10). Command 1000 is reserved for setting the internal
REF register (see Table 8). Table 12 shows how the state of the
bits in the input shift register corresponds to the mode of
operation of the device.
POWER-ON RESET
The AD5628/AD5648/AD5668 family contains a power-on
reset circuit that controls the output voltage during power-up.
The AD5628/AD5648/AD5668-1, -2 DAC output powers up to
0 V, and the AD5668-3 DAC output powers up to midscale. The
output remains powered up at this level until a valid write
sequence is made to the DAC. This is useful in applications
where it is important to know the state of the output of the DAC
while it is in the process of powering up. There is also a software
executable reset function that resets the DAC to the power-on
reset code. Command 0111 is reserved for this reset function
(see Table 8). Any events on
LDAC
or
CLR
during power-on
reset are ignored.
POWER-DOWN MODES
The AD5628/AD5648/AD5668 contain four separate modes
of operation. Command 0100 is reserved for the power-down
function (see Table 8). These modes are software-programmable
by setting two bits, Bit DB9 and Bit DB8, in the control register.
Table 12 shows how the state of the bits corresponds to the
mode of operation of the device. Any or all DACs (DAC H to
DAC A) can be powered down to the selected mode by setting
the corresponding eight bits (DB7 to DB0) to 1. See Table 13 for
the contents of the input shift register during power-down/power-
up operation. When using the internal reference, only all channel
power-down to the selected modes is supported.
When both bits are set to 0, the part works normally with its
normal power consumption of 1.3 mA at 5 V. However, for the
three power-down modes, the supply current falls to 0.4 µA at
5 V (0.2 µA at 3 V). Not only does the supply current fall, but
the output stage is also internally switched from the output of
the amplifier to a resistor network of known values. This has the
advantage that the output impedance of the part is known while
the part is in power-down mode. There are three different
options. The output is connected internally to GND through
either a 1 kΩ or a 100 kΩ resistor, or it is left open-circuited
(three-state). The output stage is illustrated in Figure 61.
The bias generator of the selected DAC(s), output amplifier,
resistor string, and other associated linear circuitry are shut
down when the power-down mode is activated. The internal
reference is powered down only when all channels are powered
down. However, the contents of the DAC register are unaffected
when in power-down. The time to exit power-down is typically
4 µs for V
DD
= 5 V and for V
DD
= 3 V. See Figure 41 for a plot.
Any combination of DACs can be powered up by setting PD1
and PD0 to 0 (normal operation). The output powers up to the
value in the input register (
LDAC
low) or to the value in the
DAC register before powering down (
LDAC
high).
CLEAR CODE REGISTER
The AD5628/AD5648/AD5668 have a hardware
CLR
pin that
is an asynchronous clear input. The
CLR
input is falling edge
sensitive. Bringing the
CLR
line low clears the contents of the
input register and the DAC registers to the data contained in
the user-configurable
CLR
register and sets the analog outputs
accordingly. This function can be used in system calibration to load
zero scale, midscale, or full scale to all channels together. These
clear code values are user-programmable by setting two bits,
Bit DB1 and Bit DB0, in the
CLR
control register (see Table 14).
The default setting clears the outputs to 0 V. Command 0101 is
reserved for loading the clear code register (see Table 8).
The part exits clear code mode on the 32
nd
falling edge of the next
write to the part. If
CLR
is activated during a write sequence, the
write is aborted.
The
CLR
pulse activation time—the falling edge of
CLR
to
when the output starts to change—is typically 280 ns. However, if
outside the DAC linear region, it typically takes 520 ns after
executing
CLR
for the output to start changing (see Figure 51).
See Table 15 for contents of the input shift register during the
loading clear code register operation.