Datasheet

Data Sheet AD5624R/AD5644R/AD5664R
Rev. C | Page 21 of 28
At this stage, the
SYNC
line can be kept low or be brought high. In
either case, it must be brought high for a minimum of 15 ns before
the next write sequence so that a falling edge of
SYNC
can initiate
the next write sequence.
Because the
SYNC
buffer draws more current when V
IN
= 2 V
than it does when V
IN
= 0.8 V,
SYNC
should be idled low
between write sequences for even lower power operation. As
mentioned previously, it must, however, be brought high again
just before the next write sequence.
INPUT SHIFT REGISTER
The input shift register is 24 bits wide (see Figure 53). The first
two bits are don’t care bits. The next three are the command
bits, C2 to C0 (see Table 8), followed by the 3-bit DAC address,
A2 to A0 (see Table 9), and then the 16-, 14-, 12-bit data-word.
The data-word comprises the 16-, 14-, 12-bit input code
followed by 0, 2, or 4 don’t care bits, for the AD5664R,
AD5644R, and AD5624R, respectively (see Figure 53, Figure 54,
and Figure 55). These data bits are transferred to the DAC
register on the 24
th
falling edge of SCLK.
Table 8. Command Definition
C2 C1 C0 Command
0 0 0 Write to input register n
0 0 1 Update DAC register n
0 1 0 Write to input register n, update all
(software LDAC)
0 1 1 Write to and update DAC channel n
1 0 0 Power down DAC (power-up)
1
0
1
Reset
1 1 0 LDAC register setup
1 1 1 Internal reference setup (on/off)
Table 9. Address Command
A2
A1
A0
Address (n)
0 0 0 DAC A
0
0
1
DAC B
0 1 0 DAC C
0 1 1 DAC D
1 1 1 All DACs
SYNC
INTERRUPT
In a normal write sequence, the
SYNC
line is kept low for at least
24 falling edges of SCLK, and the DAC is updated on the 24
th
falling edge. However, if
SYNC
is brought high before the 24
th
falling edge, then this acts as an interrupt to the write sequence.
The input shift register is reset and the write sequence is seen as
invalid. Neither an update of the DAC register contents nor a
change in the operating mode occurs (see
Figure 56).
Figure 53. AD5664R Input Shift Register Contents
Figure 54. AD5644R Input Shift Register Contents
Figure 55. AD5624R Input Shift Register Contents
Figure 56.
SYNC
Interrupt Facility
X
X
C2
C1
C0
A2
A1
A0
D15
D14
D13
D12 D11
D10
D9 D8
D7
D6
D5
D4
D3
D2
D1
D0
DB23 (MSB)
DB0 (LSB)
COMMAND BITS
ADDRESS BITS
DATA BITS
05856-034
X X C2
C1 C0 A2
A1 A0
X X
D11 D10D13 D12 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DB23 (MSB) DB0 (LSB)
COMMAND BITS ADDRESS BITS
DATA BITS
05856-035
X X C2 C1
C0 A2 A1 A0
X X X X
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DB23 (MSB) DB0 (LSB)
COMMAND BITS ADDRESS BITS
DATA BITS
05856-036
DIN
DB23 DB23 DB0DB0
VALID WRITE SEQUENCE, OUTPUT UPDATES
ON THE 24
TH
FALLING EDGE
SYNC
SCLK
INVALID WRITE SEQUENCE:
SYNC HIGH BEFORE 24
TH
FALLING EDGE
05856-037