Datasheet

Data Sheet AD5623R/AD5643R/AD5663R
Rev. E | Page 9 of 32
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
05858-003
1
V
OUT
A
10
V
REFIN
/V
REFOUT
2
V
OUT
B
9
V
DD
3
GND
8
DIN
4
LDAC
7
SCLK
5
CLR
6
SYNC
AD5623R/
AD5643R/
AD5663R
TOP VIEW
(Not to Scale)
NOTE:
EXPOSED PAD TIED TO GND ON
LFCSP PACKAGE.
Figure 3. Pin Configuration
Table 7. Pin Function Descriptions
Pin No. Mnemonic Description
1 V
OUT
A Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
2 V
OUT
B Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
3 GND Ground. Reference point for all circuitry on the part.
4
LDAC
Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data.
This allows simultaneous update of all DAC outputs. Alternatively, this pin can be tied permanently low.
5
CLR
Asynchronous Clear Input. The
CLR
input is falling edge sensitive. While
CLR
is low, all
LDAC
pulses are
ignored. When
CLR
is activated, zero scale is loaded to all input and DAC registers. This clears the output to 0 V.
The part exits clear code mode on the 24th falling edge of the next write to the part. If
CLR
is activated during
a write sequence, the write is aborted.
6
SYNC
Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data.
When
SYNC
goes low, it enables the input shift register, and data is transferred in on the falling edges of the
following clocks. The DAC is updated following the 24th clock cycle unless
SYNC
is taken high before this edge,
in which case the rising edge of
SYNC
acts as an interrupt and the write sequence is ignored by the DAC.
7 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input.
Data can be transferred at rates up to 50 MHz.
8 DIN Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the falling edge
of the serial clock input.
9 V
DD
Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be decoupled with
a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND.
10 V
REFIN
/V
REFOUT
Common Reference Input/Reference Output. When the internal reference is selected, this is the reference output
pin. When using an external reference, this is the reference input pin. The default for this pin is a reference input.