Datasheet

Data Sheet AD5623R/AD5643R/AD5663R
Rev. E | Page 7 of 32
TIMING CHARACTERISTICS
All input signals are specified with t
R
= t
F
= 1 ns/V (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
V
DD
= 2.7 V to 5.5 V; all specifications T
MIN
to T
MAX
, unless otherwise noted.
1
Table 5.
Limit at T
MIN
, T
MAX
Parameter V
DD
= 2.7 V to 5.5 V Unit Conditions/Comments
t
1
2
20 ns min SCLK cycle time
t
2
9 ns min SCLK high time
t
3
9 ns min SCLK low time
t
4
13 ns min
SYNC
to SCLK falling edge setup time
t
5
5 ns min Data setup time
t
6
5 ns min Data hold time
t
7
0 ns min
SCLK falling edge to
SYNC
rising edge
t
8
15 ns min
Minimum
SYNC
high time
t
9
13 ns min
SYNC
rising edge to SCLK fall ignore
t
10
0 ns min
SCLK falling edge to
SYNC
fall ignore
t
11
10 ns min
LDAC
pulse width low
t
12
15 ns min
SCLK falling edge to
LDAC
rising edge
t
13
5 ns min
CLR
pulse width low
t
14
0 ns min
SCLK falling edge to
LDAC
falling edge
t
15
300 ns max
CLR
pulse activation time
1
Guaranteed by design and characterization, not production tested.
2
Maximum SCLK frequency is 50 MHz at V
DD
= 2.7 V to 5.5 V.
TIMING DIAGRAM
05858-002
t
4
t
3
SCLK
SYNC
DIN
t
1
t
2
t
5
t
6
t
7
t
8
DB23
t
9
t
10
t
11
t
12
LDAC
1
LDAC
2
t
14
1
ASYNCHRONOUS LDAC UPDATE MODE.
2
SYNCHRONOUS LDAC UPDATE MODE.
CLR
t
13
t
15
V
OUT
DB0
Figure 2. Serial Write Operation