Datasheet

Data Sheet AD5623R/AD5643R/AD5663R
Rev. E | Page 23 of 32
Table 13. 24-Bit Input Shift Register Contents of Power Up/Down Function
MSB LSB
DB23 to
DB22 DB21 DB20 DB19 DB18 DB17 DB16
DB15 to
DB6 DB5 DB4 DB3 DB2 DB1 DB0
x 1 0 0 x x x x PD1 PD0 x x DAC B DAC A
Don’t
care
Command bits (C2 to C0) Address bits (A2 to A0)
Don’t care
Don’t
care
Power-down
mode
Don’t care Power down/Power up
channel selection;
set bit to 1 to select
channel
Table 14. 24-Bit Input Shift Register Contents for
LDAC
Setup Command
MSB LSB
DB23 to
DB22
DB21 DB20 DB19 DB110 DB17 DB16 DB15 to DB2 DB1 DB0
x
1
1
0
x
x
x
x
DAC B
DAC A
Don’t care Command bits (C2 to C0) Address bits (A3 to A0)
Don’t care
Don’t care Set DAC to 0 or 1 for required
mode of operation
LDAC
FUNCTION
The AD5623R/AD5643R/AD5663R DACs have double-
buffered interfaces consisting of two banks of registers: input
registers and DAC registers. The input registers are connected
directly to the input shift register, and the digital code is
transferred to the relevant input register on completion of a
valid write sequence. The DAC registers contain the digital code
used by the resistor strings.
Access to the DAC registers is controlled by the
LDAC
pin.
When the
LDAC
pin is high, the DAC registers are latched and
the input registers can change state without affecting the
contents of the DAC registers. When
LDAC
is brought low,
however, the DAC registers become transparent and the
contents of the input registers are transferred to them. The
double-buffered interface is useful if the user requires
simultaneous updating of all DAC outputs. The user can write
to one of the input registers individually and then, by bringing
LDAC
low when writing to the other DAC input register, all
outputs will update simultaneously.
These parts each contain an extra feature whereby a DAC
register is not updated unless its input register has been updated
since the last time
LDAC
was brought low. Normally, when
LDAC
is brought low, the DAC registers are filled with the contents of
the input registers. In the case of the AD5623R/AD5643R/
AD5663R, the DAC register updates only if the input register
has changed since the last time the DAC register was updated,
thereby removing unnecessary digital crosstalk.
The outputs of all DACs can be simultaneously updated, using
the hardware
LDAC
pin.
Synchronous
LDAC
The DAC registers are updated after new data is read in on the
falling edge of the 24th SCLK pulse.
LDAC
can be permanently
low or pulsed as shown in Figure 2.
Asynchronous
LDAC
The outputs are not updated at the same time that the input
registers are written to. When
LDAC
goes low, the DAC
registers are updated with the contents of the input register.
The
LDAC
register gives the user full flexibility and control over
the hardware
LDAC
pin. This register allows the user to select
which combination of channels to simultaneously update when
the hardware
LDAC
pin is executed. Setting the
LDAC
bit
register to 0 for a DAC channel means that the update of this
channel is controlled by the
LDAC
pin. If this bit is set to 1, this
channel synchronously updates; that is, the DAC register is
updated after new data is read in, regardless of the state of the
LDAC
pin. It effectively sees the
LDAC
pin as being pulled low.
See Table 15 for the
LDAC
register mode of operation. This
flexibility is useful in applications where the user wants to
simultaneously update select channels while the rest of the
channels are synchronously updating.
Writing to the DAC using Command 110 loads the 2-bit
LDAC
register [DB1:DB0]. The default for each channel is 0; that is,
the
LDAC
pin works normally. Setting the bits to 1 means the
DAC register is updated, regardless of the state of the
LDAC
pin. See Table 14 for contents of the input shift register during
the
LDAC
register setup command.
Table 15.
LDAC
Register Mode of Operation
LDAC
Bits
(DB1 to DB0)
LDAC
Pin
LDAC
Operation
0 1/0 Determined by
LDAC
pin
1 x = don’t care The DAC registers are updated
after new data is read in on the
falling edge of the 24th SCLK
pulse.