Datasheet

Data Sheet AD5623R/AD5643R/AD5663R
Rev. E | Page 21 of 32
At this stage, the
SYNC
line can be kept low or be brought high.
In either case, it must be brought high for a minimum of 15 ns
before the next write sequence, so that a falling edge of
SYNC
can initiate the next write sequence.
Because the
SYNC
buffer draws more current when V
IN
= 2 V
than it does when V
IN
= 0.8 V,
SYNC
should be idled low between
write sequences for even lower power operation. As mentioned
previously, it must, however, be brought high again just before
the next write sequence.
INPUT SHIFT REGISTER
The input shift register is 24 bits wide (see Figure 52). The first
two bits are don’t cares. The next three are Command Bit C2 to
Command Bit C0 (see Table 8), followed by the 3-bit DAC
Address A2 to DAC Address A0 (see Table 9), and, finally, the
16-, 14-, and 12-bit data-word.
The data-word comprises the 16-, 14-, and 12-bit input codes,
followed by zero, two, or four don’t care bits, for the AD5663R,
AD5643R, and AD5623R, respectively (see Figure 51, Figure 52,
and Figure 53). The data bits are transferred to the DAC register
on the 24th falling edge of SCLK.
Table 8. Command Definition
C2 C1 C0 Command
0 0 0 Write to Input Register n
0 0 1 Update DAC Register n
0 1 0 Write to Input Register n, update all
(software
LDAC
)
0 1 1 Write to and update DAC Channel n
1 0 0 Power down DAC (power up)
1 0 1 Reset
1 1 0
LDAC
register setup
1 1 1 Internal reference setup (on/off)
Table 9. Address Command
A2 A1 A0 ADDRESS (n)
0 0 0 DAC A
0 0 1 DAC B
0 1 0 Reserved
0 1 1 Reserved
1 1 1 All DACs
SYNC
INTERRUPT
In a normal write sequence, the
SYNC
line is kept low for at
least 24 falling edges of SCLK, and the DAC is updated on the
24th falling edge. However, if
SYNC
is brought high before the
24th falling edge, this acts as an interrupt to the write sequence.
The shift register is reset, and the write sequence is seen as
invalid. Neither an update of the DAC register contents nor a
change in the operating mode occurs (see
Figure 54).
X X C2 C1 C0 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DB23 (MSB) DB0 (LSB)
COMMAND BITS ADDRESS BITS
DATA BITS
05858-034
Figure 51. AD5663R Input Shift Register Contents
X X C2 C1 C0 A2 A1 A0 X XD11 D10D13 D12 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DB23 (MSB) DB0 (LSB)
COMMAND BITS
ADDRESS BITS
DATA BITS
05858-071
Figure 52. AD5643R Input Shift Register Contents
X X C2 C1 C0 A2 A1 A0 X X X XD11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DB23 (MSB) DB0 (LSB)
COMMAND BITS ADDRESS BITS
DATA BITS
05858-072
Figure 53. AD5623R Input Shift Register Contents
DIN
DB23 DB23 DB0DB0
VALID WRITE SEQUENCE, OUTPUT UPDATES
ON THE 24
TH
FALLING EDGE
SYNC
SCLK
INVALID WRITE SEQUENCE:
SYNC HIGH BEFORE 24
TH
FALLING EDGE
05858-035
Figure 54.
SYNC
Interrupt Facility