Datasheet

AD5641 Data Sheet
Rev. D | Page 6 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD5641
TOP VIEW
(Not to Scale)
V
OUT
SYNC
16
GNDSCLK
25
SDIN
V
DD
34
04611-003
Figure 3. 6-Lead SC70 Pin Configuration
04611-045
AD5641
TOP VIEW
(Not to Scale)
1V
DD
3SDIN
2
S
CLK
NOTES:
1. CONNECT THE EXPOSED PAD TO GND.
6V
OUT
4 SYNC
5GND
Figure 4. 6-Lead LFCSP Pin Configuration
Table 5. Pin Function Descriptions
SC70
Pin No.
LFCSP
Pin No. Mnemonic Description
1 4
SYNC
Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input
data. When SYNC
goes low, it enables the input shift register and data is transferred in on the falling
edges of the clocks that follow. The DAC is updated following the 16
th
clock cycle unless SYNC is
taken high before this edge, in which case the rising edge of SYNC
acts as an interrupt and the write
sequence is ignored by the DAC.
2 2 SCLK
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock
input. Data can be transferred at rates up to 30 MHz.
3 3 SDIN
Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling
edge of the serial clock input.
4 1 V
DD
Power Supply Input. The AD5641 can be operated from 2.7 V to 5.5 V. V
DD
should be decoupled to
GND.
5 5 GND Ground Reference Point for All Circuitry on the AD5641.
6 6 V
OUT
Analog Output Voltage from the DAC. The output amplifier has rail-to-rail operation.
EP Exposed Pad. Connect to GND.