Datasheet

AD5641 Data Sheet
Rev. D | Page 14 of 20
DATA BITS
DB15 (MSB) DB0 (LSB)
PD1 PD0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
NORMAL OPERATION
1 kΩ TO GND
100 kΩ TO GND
THREE-STATE
POWER-DOWN MODES
0
0
1
1
0
1
0
1
04611-033
Figure 35. Input Register Contents
04611-034
DB15 DB16 DB0DB0
INVALID WRITE SEQUENCE:
SYNC HIGH BEFORE 16
TH
FALLING EDGE
VALID WRITE SEQUENCE, OUTPUT UPDATES
ON THE 16
TH
FALLING EDGE
SYNC
SCLK
SDIN
Figure 36.
SYNC
Interrupt Facility
POWER-ON RESET
The AD5641 contains a power-on reset circuit that controls the
output voltage during power-up. The DAC register is filled with
0s and the output voltage is 0 V. It remains there until a valid
write sequence is made to the DAC. This is useful in applica-
tions in which it is important to know the state of the DAC
output while it is in the process of powering up.
POWER-DOWN MODES
The AD5641 has four separate modes of operation. These
modes are software programmable by setting two bits (DB15
and DB14) in the control register. Table 6 shows how the state
of the bits corresponds to the operating mode of the device.
Table 6. Operating Modes for the AD5641
DB15 DB14 Operating Mode
0 0 Normal operation
Power-down mode:
0 1 1 kΩ to GND
1 0 100 kΩ to GND
1 1 Three-state
When both bits are set to 0, the part has normal power
consumption of 100 µA maximum at 5 V. However, for the
three power-down modes, the supply current falls to typically
0.2 µA at 3 V.
Not only does the supply current fall, but the output stage is
also internally switched from the output of the amplifier to a
resistor network of known values. This has the advantage that
the output impedance of the part is known while the part is in
power-down mode. There are three different options: the
output is connected internally to GND through either a 1 kΩ
resistor or a 100 kΩ resistor, or the output is left open-circuited
(three-stated). Figure 37 shows the output stage.
POWER-DOWN
CIRCUITRY
RESISTOR
NETWORK
V
OUT
RESISTOR
STRING DAC
AMPLIFIER
04611-035
Figure 37. Output Stage During Power-Down
The bias generator, output amplifier, resistor string, and other
associated linear circuitry are all shut down when power-down
mode is activated. However, the contents of the DAC register
are unaffected when in power-down. The time to exit power-
down is typically 13 µs for V
DD
= 5 V and 16 µs for V
DD
= 3 V.
See Figure 29 for a plot.