Datasheet

Data Sheet AD5620/AD5640/AD5660
Rev. G | Page 9 of 28
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
SYNC
04539-003
V
DD
1
V
REFOUT
2
V
FB
3
V
OUT
4
GND8
DIN7
SCLK6
5
AD5620/
AD5640/
AD5660
TOP VIEW
(Not to Scale)
Figure 3. SOT-23 Pin Configuration
SYNC
04539-004
V
DD
1
V
REFOUT
2
V
FB
3
V
OUT
4
GND 8
DIN
7
SCLK 6
5
AD5620/
AD5640/
AD5660
TOP VIEW
(Not to Scale)
Figure 4. MSOP Pin Configuration
3
4
1
2
6
5
8
7
AD5620/
AD5640/
AD5660
TOP VIEW
V
DD
V
REFOUT
V
FB
V
OUT
GND
DIN
SCLK
SYNC
04539-105
Figure 5. LFCSP Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description
1 V
DD
Power Supply Input. These parts can operate from 2.7 V to 5.5 V. V
DD
should be decoupled to GND.
2 V
REFOUT
Reference Voltage Output.
3 V
FB
Feedback Connection for the Output Amplifier. V
FB
should be connected to V
OUT
for normal operation.
4 V
OUT
Analog Output Voltage from DAC. The output amplifier has rail-to-rail operation.
5
SYNC
Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When
SYNC
goes low, it enables the input shift register and data is transferred in on the falling edges of the following
clocks. The DAC is updated following the 24
th
clock cycle for the AD5660 and the 16
th
clock cycle for
AD5620/AD5640 unless SYNC is taken high before this edge. In this case, the rising edge of SYNC acts as an
interrupt, and the write sequence is ignored by the DAC.
6 SCLK
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data
can be transferred at rates up to 30 MHz.
7 DIN
Serial Data Input. The AD5660 has a 24-bit shift register, and the AD5620/AD5640 have a 16-bit shift register.
Data is clocked into the register on the falling edge of the serial clock input.
8 GND Ground Reference Point for all Circuitry on the Part.