Datasheet
AD5627R/AD5647R/AD5667R, AD5627/AD5667
Rev. 0 | Page 26 of 32
POWER-ON RESET AND SOFTWARE RESET
The AD56x7R/AD56x7 contain a power-on reset circuit that
controls the output voltage during power-up. The device powers
up to 0 V and the output remains powered up at this level until
a valid write sequence is made to the DAC. This is useful in
applications where it is important to know the state of the
output of the DAC while it is in the process of powering up. Any
events on
LDAC
or
CLR
during power-on reset are ignored.
There is also a software reset function. Command 101 is the
software reset command. The software reset command contains
two reset modes that are software programmable by setting Bit
DB0 in the input shift register.
Table 12 shows how the state of the bit corresponds to the
software reset modes of operation of the devices.
Figure 64
shows the contents of the input shift register during the
software reset mode of operation.
Table 12. Software Reset Modes for the AD56x7R/AD56x7
DB0 Registers reset to zero
0 DAC register
Input shift register
1 (Power-On Reset) DAC register
Input shift register
LDAC register
Power-down register
Internal reference setup register
CLEAR PIN (CLR)
The AD56x7R/AD56x7 has an asynchronous clear input. The
CLR
input is falling-edge sensitive. While
CLR
is low, all
LDAC
pulses are ignored. When
CLR
is activated, zero scale is loaded
to all input and DAC registers. This clears the output to 0 V. The
part exits clear code mode on the on the falling edge of the 9
th
clock pulse of the last byte of valid write. If
CLR
is activated
during a write sequence, the write is aborted. If
CLR
is activated
during high speed mode, the part exits high speed mode to
standard/fast mode.
INTERNAL REFERENCE SETUP (R VERSIONS)
The on-chip reference is off at power-up by default. It can be
turned on by sending the reference setup command (111) and
setting DB0 in the input shift register.
Table 13 shows how the
state of the bit corresponds to the mode of operation. See
Figure 66
for the contents of the input shift register during the internal
reference setup command.
Table 13. Reference Setup Command
DB0 Action
0 Internal reference off (default)
1 Internal reference on
X S C2 C1 C0 A2 A1 A0 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 X
RESERVED
DON’T
CARE
1 0 1 X X X X X X X X X X X X X X X X X X RST
COMMAND
DAC ADDRESS
(DON’T CARE)
DON’T CARE DON’T CARE
RESET
MODE
06342-113
Figure 64. Software Reset Command
R S C2 C1 C0 A2 A1 A0 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 X
RESERVED
DON’T
CARE
1 0 0 X X X X X X X X X X X X X PD1 PD0 X X DACB DACA
COMMAND
DAC ADDRESS
(DON’T CARE)
DON’T CARE DON’T CARE
POWER-
DOWN MODE
DON’T CARE
DAC SELECT
(1 = DAC SELECTED)
06342-112
Figure 65. Power Up/Down Command
R S C2 C1 C0 A2 A1 A0 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 X
RESERVED
DON’T
CARE
1 1 1 X X X X X X X X X X X X X X X X X X REF
COMMAND
DAC ADDRESS
(DON’T CARE)
DON’T CARE DON’T CARE
REFERENCE
MODE
06342-114
Figure 66. Reference Setup Command