Datasheet

AD5627R/AD5647R/AD5667R, AD5627/AD5667
Rev. 0 | Page 24 of 32
SLAVE
ADDRESS
COMMAND
BYTE
MOST SIGNIFICANT
DATA BYTE
MOST SIGNIFICANT
DATA BYTE
LEAST SIGNIFICANT
DATA BYTE
LEAST SIGNIFICANT
DATA BYTE
S = 1
BLOCK 1
S = 1
BLOCK 2
MOST SIGNIFICANT
DATA BYTE
LEAST SIGNIFICANT
DATA BYTE
STOP
S = 1
BLOCK n
06342-106
Figure 57. Multiple Block Write with Initial Command Byte Only (S = 1)
SLAVE
ADDRESS
COMMAND
BYTE
MOST SIGNIFICANT
DATA BYTE
COMMAND
BYTE
LEAST SIGNIFICANT
DATA BYTE
MOST SIGNIFICANT
DATA BYTE
LEAST SIGNIFICANT
DATA BYTE
S = 0
BLOCK 1
S = 0
BLOCK 2
MOST SIGNIFICANT
DATA BYTE
COMMAND
BYTE
LEAST SIGNIFICANT
DATA BYTE
STOP
S = 0
BLOCK n
06342-107
Figure 58. Multiple Block Write with Command Byte in Each Block (S = 0)
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
R S
RESERVED
BYTE
SELECTION
C2 C1 C0 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
COMMAND DAC ADDRESS DAC DATA DAC DATA
COMMAND BYTE DATA HIGH BYTE DATA LOW BYTE
06342-108
Figure 59. AD5667R/AD5667 Input Shift Register (16-Bit DAC)
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
R S
RESERVED
BYTE
SELECTION
C2 C1 C0 A2 A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X
COMMAND DAC ADDRESS DAC DATA DAC DATA
COMMAND BYTE DATA HIGH BYTE DATA LOW BYTE
06342-109
Figure 60. AD5647R Input Shift Register (14-Bit DAC)
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
R S
RESERVED
BYTE
SELECTION
C2 C1 C0 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X
COMMAND DAC ADDRESS DAC DATA DAC DATA
COMMAND BYTE DATA HIGH BYTE DATA LOW BYTE
06342-110
Figure 61. AD5627R/AD5627 Input Shift Register (12-Bit DAC)