Datasheet

AD5626
Rev. A | Page 11 of 20
voltage vs. load current plot, shown in Figure 11, provides
information for operation below V
DD
= 4.75 V.
TIMING AND CONTROL
The AD5626 has a separate serial input register from the
12-bit DAC register that allows preloading of a new data value
into the serial register without disturbing the present DAC
output voltage. After the new value is fully loaded in the serial
input register, it can be asynchronously transferred to the DAC
register by strobing the
LDAC
pin. The DAC register uses a
level sensitive
LDAC
strobe that should be returned high before
any new data is loaded into the serial input register. At any time,
the contents of the DAC register can be reset to zero by strobing
the
CLR
pin that causes the DAC output voltage to go to zero
volts. details all of the timing requirements together
with , the control logic truth table.
Figure 2
Table 5