Datasheet

AD5624/AD5664
Rev. 0 | Page 7 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
V
OUT
A
10
V
REF
2
V
OUT
B
9
V
DD
3
GND
8
DIN
4
V
OUT
C
7
SCLK
5
V
OUT
D
6
SYNC
AD5624/
AD5664
TOP VIEW
(Not to Scale)
0
5943-003
Figure 3. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description
1 V
OUT
A Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
2 V
OUT
B Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
3 GND Ground Reference Point for All Circuitry on the Part.
4 V
OUT
C Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
5 V
OUT
D Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
6
SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it
powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling edges
of the next 24 clocks. If
SYNC is taken high before the 24
th
falling edge, the rising edge of SYNC acts as an interrupt
and the write sequence is ignored by the device.
7 SCLK
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can
be transferred at rates up to 50 MHz.
8 DIN
Serial Data Input. This device has a 24-bit input shift register. Data is clocked into the register on the falling edge of
the serial clock input.
9 V
DD
Power Supply Input. These parts can be operated from 2.7 V to 5.5 V. The supply should be decoupled with a 10 μF
capacitor in parallel with a 0.1 μF capacitor to GND.
10 V
REF
Reference Voltage Input.