Datasheet

AD5624/AD5664
Rev. 0 | Page 5 of 24
TIMING CHARACTERISTICS
All input signals are specified with t
R
= t
F
= 1 ns/V (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2 (see Figure 2).
V
DD
= 2.7 V to 5.5 V; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 4.
Limit at T
MIN
, T
MAX
Parameter
1
V
DD
= 2.7 V to 5.5 V Unit Conditions/Comments
t
1
2
20 ns min SCLK cycle time
t
2
9 ns min SCLK high time
t
3
9 ns min SCLK low time
t
4
13 ns min
SYNC to SCLK falling edge setup time
t
5
5 ns min Data setup time
t
6
5 ns min Data hold time
t
7
0 ns min
SCLK falling edge to
SYNC rising edge
t
8
15 ns min
Minimum
SYNC high time
t
9
13 ns min
SYNC rising edge to SCLK fall ignore
t
10
0 ns min
SCLK falling edge to
SYNC fall ignore
1
Guaranteed by design and characterization, not production tested.
2
Maximum SCLK frequency is 50 MHz at V
DD
= 2.7 V to 5.5 V.
TIMING DIAGRAM
DB0DB23
t
10
SCLK
SYNC
DIN
t
1
t
9
t
7
t
2
t
3
t
6
t
5
t
4
t
8
05943-002
Figure 2. Serial Write Operation