Datasheet

Data Sheet AD5602/AD5612/AD5622
Rev. C | Page 5 of 24
Limit at T
MIN
, T
MAX
Parameter Conditions
2
Min Max Unit Description
t
8
Standard mode 4 µs t
SU;STO
, setup time for a stop condition
Fast mode 0.6 µs
High speed mode 160 ns
t
9
Standard mode 1000 ns t
RDA
, rise time of SDA signal
Fast mode 300 ns
High speed mode, C
B
= 100 pF 10 80 ns
High speed mode, C
B
= 400 pF 20 160 ns
t
10
Standard mode 300 ns t
FDA
, fall time of SDA signal
Fast mode 300 ns
High speed mode, C
B
= 100 pF 10 80 ns
High speed mode, C
B
= 400 pF 20 160 ns
t
11
Standard mode 1000 ns t
RCL
, rise time of SCL signal
Fast mode 300 ns
High speed mode, C
B
= 100 pF 10 40 ns
High speed mode, C
B
= 400 pF
20
80
ns
t
11A
Standard mode 1000 ns t
RCL1
, rise time of SCL signal after a repeated start
condition and after an acknowledge bit
Fast mode 300 ns
High speed mode, C
B
= 100 pF 10 80 ns
High speed mode, C
B
= 400 pF 20 160 ns
t
12
Standard mode 300 ns t
FCL
, fall time of SCL signal
Fast mode 300 ns
High speed mode, C
B
= 100 pF 10 40 ns
High speed mode, C
B
= 400 pF 20 80 ns
t
SP
4
Fast mode 0 50 ns Pulse width of spike suppressed
High speed mode
0
10
ns
1
See Figure 2. High speed mode timing specification applies to the AD5602-1/AD5612-1/AD5622-1 only. Standard and fast mode timing specifications apply to the
AD5602-1/AD5612-1/AD5622-1 and AD5602-2/AD5612-2/AD5622-2.
2
C
B
refers to the capacitance on the bus line.
3
The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on EMC behavior
of the part.
4
Input filtering on the SCL and SDA inputs suppress noise spikes that are less than 50 ns for fast mode or 10 ns for high speed mode.
TIMING DIAGRAM
SCL
SDA
P S S P
t
8
t
6
t
5
t
3
t
10
t
9
t
4
t
6
t
1
t
7
t
2
t
11
t
12
05446-002
Figure 2. 2-Wire Serial Interface Timing Diagram