Datasheet

AD5602/AD5612/AD5622 Data Sheet
Rev. C | Page 4 of 24
A, B, W, Y Versions
1
Parameter Min Typ Max Unit Test Conditions/Comments
POWER REQUIREMENTS
V
DD
2.7 5.5 V
I
DD
(Normal Mode) DAC active and excluding load current
V
DD
= 4.5 V to 5.5 V 75 100 µA V
IH
= V
DD
and V
IL
= GND
V
DD
= 2.7 V to 3.6 V 60 90 µA V
IH
= V
DD
and V
IL
= GND
I
DD
(All Power-Down Modes)
V
DD
= 4.5 V to 5.5 V 0.3 1 µA V
IH
= V
DD
and V
IL
= GND
V
DD
= 2.7 V to 3.6 V 0.15 1 µA V
IH
= V
DD
and V
IL
= GND
POWER EFFICIENCY
I
OUT
/I
DD
96 % I
LOAD
= 2 mA, V
DD
= 5 V
1
Temperature ranges for A, B versions: −40°C to +125°C, typical at 25°C.
2
Linearity calculated using a reduced code range 64 to 4032.
3
Guaranteed by design and characterization, not production tested.
I
2
C TIMING SPECIFICATIONS
V
DD
= 2.7 V to 5.5 V; all specifications T
MIN
to T
MAX
, f
SCL
= 3.4 MHz, unless otherwise noted.
1
Table 3.
Limit at T
MIN
, T
MAX
Parameter Conditions
2
Min Max Unit Description
f
SCL
3
Standard mode 100 KHz Serial clock frequency
Fast mode 400 KHz
High speed mode, C
B
= 100 pF 3.4 MHz
High speed mode, C
B
= 400 pF 1.7 MHz
t
1
Standard mode 4 µs t
HIGH
, SCL high time
Fast mode 0.6 µs
High speed mode, C
B
= 100 pF 60 ns
High speed mode, C
B
= 400 pF 120 ns
t
2
Standard mode 4.7 µs t
LOW
, SCL low time
Fast mode 1.3 µs
High speed mode, C
B
= 100 pF 160 ns
High speed mode, C
B
= 400 pF
320
ns
t
3
Standard mode 250 ns t
SU;DAT
, data setup time
Fast mode 100 ns
High speed mode 10 ns
t
4
Standard mode 0 3.45 µs t
HD ; DAT
, data hold time
Fast mode 0 0.9 µs
High speed mode, C
B
= 100 pF 0 70 ns
High speed mode, C
B
= 400 pF 0 150 ns
t
5
Standard mode 4.7 µs t
SU;STA,
set-up time for a repeated start condition
Fast mode 0.6 µs
High speed mode 160 ns
t
6
Standard mode
4
µs
t
HD;STA
, hold time (repeated) start condition
Fast mode 0.6 µs
High speed mode 160 ns
t
7
Standard mode 4.7 µs t
BUF
, bus free time between a stop and a start
condition
Fast mode 1.3 µs