Datasheet

AD5602/AD5612/AD5622 Data Sheet
Rev. C | Page 18 of 24
WRITE OPERATION
When writing to the AD5602/AD5612/AD5622, the user must
begin with a start command followed by an address byte (R/
W
=
0), after which the DAC acknowledges that it is prepared to
receive data by pulling SDA low.
Two bytes of data are then written to the DAC, the most
significant byte followed by the least significant byte as shown in
Figure 40; both of these data bytes are acknowledged by the
AD5602/AD5612/AD5622. A stop condition follows. The write
operations for the three DACs are shown in Figure 43, Figure 44,
and Figure 45.
SCL
SDA
START BY
MASTER
ACK. BY
AD5602
ACK. BY
AD5602
ACK. BY
AD5602
STOP BY
MASTER
FRAME 2
MOST SIGNIFICANT DATA BYTE
FRAME 1
SERIAL BUS ADDRESS BYTE
0
1 9
1
9 9
91
0 0 1 1 A1 A0 R/W 0 0 PD1 PD0 D7 D6 D5 D4
D3 D2 D1 D0 X X X X
SCL (CONTINUED)
SDA (CONTINUED)
FRAME 3
LEAST SIGNIFICANT DATA BYTE
05446-028
Figure 43. AD5602 Write Sequence
SCL
SDA
START BY
MASTER
ACK. BY
AD5612
ACK. BY
AD5612
ACK. BY
AD5612
STOP BY
MASTER
FRAME 2
MOST SIGNIFICANT DATA BYTE
FRAME 1
SERIAL BUS ADDRESS BYTE
0
1 9
1
9 9
91
0 0 1 1 A1 A0 R/W 0 0 PD1 PD0 D9 D8 D7 D6
D5 D4 D3 D2 D1 D0 X X
SCL (CONTINUED)
SDA (CONTINUED)
FRAME 3
LEAST SIGNIFICANT DATA BYTE
05446-029
Figure 44. AD5612 Write Sequence
SCL
SDA
START BY
MASTER
ACK. BY
AD5622
ACK. BY
AD5622
ACK. BY
AD5622
STOP BY
MASTER
FRAME 2
MOST SIGNIFICANT DATA BYTE
FRAME 1
SERIAL BUS ADDRESS BYTE
0
1 9
1
9 9
91
0 0 1 1 A1 A0 R/W 0 0 PD1 PD0 D11 D10 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
SCL (CONTINUED)
SDA (CONTINUED)
FRAME 3
LEAST SIGNIFICANT DATA BYTE
05446-030
Figure 45. AD5622 Write Sequence