Datasheet

Data Sheet AD5602/AD5612/AD5622
Rev. C | Page 15 of 24
THEORY OF OPERATION
D/A SECTION
The AD5602/AD5612/AD5622 DACs are fabricated on a
CMOS process. The architecture consists of a string DACs
followed by an output buffer amplifier. Figure 37 shows a block
diagram of the DAC architecture.
V
DD
V
OUT
GND
RESISTOR
NETWORK
REF (+)
REF (–)
OUTPUT
AMPLIFIER
DAC REGISTER
05446-022
Figure 37. DAC Architecture
Since the input coding to the DAC is straight binary, the ideal
output voltage is given by






×=
n
DDOUT
D
VV
2
where:
D is the decimal equivalent of the binary code that is loaded
to the DAC register; it can range from 0 to 255 (AD5602),
0 to 1023 (AD5612), or 0 to 4095 (AD5622).
n is the bit resolution of the DAC.
RESISTOR STRING
The resistor string structure is shown in Figure 38. It is simply a
string of resistors, each of value R. The code loaded to the DAC
register determines at which node on the string the voltage is
tapped off to be fed into the output amplifier. The voltage is
tapped off by closing one of the switches connecting the string
to the amplifier. Because it is a string of resistors, it is
guaranteed monotonic.
R
R
R
R
R
TO OUTPUT
AMPLIFIER
05446-023
Figure 38. Resistor String Structure
OUTPUT AMPLIFIER
The output buffer amplifier is capable of generating rail-to-rail
voltages on its output, giving an output range of 0 V to V
DD
. It is
capable of driving a load of 2 kΩ in parallel with 1000 pF to
GND. The source and sink capabilities of the output amplifier
can be seen in Figure 27. The slew rate is 0.5 V/µs with a half-
scale settling time of 5 µs with the output unloaded.