Datasheet

AD5590
Rev. A | Page 9 of 44
TIMING SPECIFICATIONS
ADC Timing Characteristics
ADCV
DD
= 2.7 V to 5.25 V, V
DRIVE
≤ ADCV
DD
, V
REFA
= 2.5 V; All specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 5.
Parameter
1
Limit at T
MIN
, T
MAX
; ADCV
DD
= 5 V Unit Conditions/Comments
f
SCLK
2
10 kHz min
20 MHz min
t
CONVERT
16 × t
ASCLK
MHz max
t
QUIET
50 ns min
t
2
10 ns min
ASYNC
to ASCLK setup time
t
3
3
14 ns max Delay from
ASYNC
until ADOUT three-state disabled
t
3
b
4
20 ns min Data hold time
t
4
3
40 ns max Data access time after ASCLK falling edge
t
5
0.4 × t
ASCLK
ns min ASCLK low pulse width
t
6
0.4 × t
ASCLK
ns min ASCLK high pulse width
t
7
15 ns min ASCLK to ADOUT valid hold time
t
8
5
15/50 ns min/max ASCLK falling edge to ADOUT high impedance
t
9
20 ns min ADIN setup time prior to ASCLK falling edge
t
10
5 ns min ADIN Hold time prior to ASCLK falling edge
t
11
20 ns min 16
th
ASCLK falling edge to
ASYNC
high
t
12
1 µs max Power-up time from full power-down/autoshutdown/
autostandby modes
1
Guaranteed by design and characterization. Not production tested. All input signals are specified with tr = tf = 5 ns (10% to 90% of ADCV
DD
) and timed from a voltage
level of 1.6 V.
2
Maximum ASCLK frequency is 50 MHz at ADCV
DD
= 2.7 V to 5.5 V. Guaranteed by design and characterization; not production tested.
3
Measured with the load circuit of Figure 3 and defined as the time required for the output to cross 0.4 V or 0.7 × V
DRIVE
.
4
t
3
b represents a worst-case figure for having ADD3 available on the ADOUT line, that is, if the ADC goes back into three-state at the end of a conversion and some
other device takes control of the bus between conversions, the user needs to wait a maximum time of t
3
b before having ADD3 valid on the ADOUT line. If the ADOUT
line is weakly driven to ADD3 between conversions, then the user typically needs to wait 17 ns at 3 V and 12 ns at 5 V after the
ASYNC
falling edge before seeing ADD3
valid on ADOUT.
5
t
8
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 3. The measured number is then extrapolated
back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t
8
, quoted in the timing characteristics, is the true bus relinquish
time of the part and is independent of bus loading.
ASCLK
ADOUT
ADIN
ASYNC
WRITE SEQ ADD3 ADD2 ADD1 ADD0 DONTC DONTC DONTC
ADD2 ADD1 ADD0 DB11 DB10 DB2 DB1 DB0
B
t
2
t
3
b
t
3
1 2 3 4 5 6 13 14 15 16
t
9
t
10
t
8
t
4
t
7
t
6
t
5
t
11
t
QUIET
t
CONVERT
THREE-
STATE
THREE-
STATE
ADD3
FOUR IDENTIFICATION BITS
07691-002
Figure 2. ADC Timing Characteristics
200µA I
OL
200µA I
OH
1.6V
TO OUTPUT
PIN
C
L
25pF
07691-003
Figure 3. Load Circuit for ADC Digital Output Timing Specifications