Datasheet

AD5590
Rev. A | Page 5 of 44
Parameter Min Typ Max Unit Test Conditions/Comments
2
LOGIC INPUTS
Input High Voltage, V
INH
0.7 × V
DRIVE
V
Input Low Voltage, V
INL
0.3 × V
DRIVE
V
Input Current, I
IN
−1 +1 µA Typically 10 nA
Input Capacitance, C
IN
1, 4
10
pF
LOGIC OUTPUTS
Output High Voltage, V
OH
V
DRIVE
− 0.2 V I
SOURCE
= 200 µA; V
DD
= 2.7 V to 5.25 V
Output Low Voltage, V
OL
0.4 V I
SINK
= 200 µA
Floating State Leakage Current ±10 µA weak/
TRI
bit set to 0
Floating State Output Capacitance
4
10 pF weak/
TRI
bit set to 0
Output Coding Straight (Natural) Binary coding bit set to 1
Twos Complement coding bit set to 0
CONVERSION RATE
4
Conversion Time 800 ns 16 ASCLK cycles, ASCLK = 20 MHz
Track-and-Hold Acquisition Time
3
300 ns Sine wave input
300 ns Full-scale step input
Throughput Rate 1 MSPS @ 5 V (see the Serial Interface section)
POWER REQUIREMENTS
ADCV
DD
2.7
5.25
V
V
DRIVE
2.7 5.25 V
I
DRIVE
0.15 µA
I
DD
5
Digital inputs = 0 V or V
DRIVE
Normal Mode, Static 750 µA V
DD
= 4.75 V to 5.25 V, ASCLK on or off
Normal Mode, Operational
(f
S
= Maximum Throughput)
2.5 mA V
DD
= 4.75 V to 5.25 V, f
SCLK
= 20 MHz
Autostandby Mode 1.55 mA f
SAMPLE
= 500 kSPS
100 µA Static
Autoshutdown Mode 960 µA f
SAMPLE
= 250 kSPS
0.5 µA Static
Full Shutdown Mode
0.02
0.5
µA
ASCLK on or off
Power Dissipation
Normal Mode, Operational 12.5 mW ADCV
DD
= 5 V, f
SCLK
= 20 MHz
Autostandby Mode, Static 500 µW ADCV
DD
= 5 V
Autoshutdown Mode, Static 2.5 µW ADCV
DD
= 5 V
Full Shutdown Mode 2.5 µW ADCV
DD
= 5 V
1
Specifications apply for f
SCLK
up to 20 MHz. For serial interfacing requirements, see the Timing Specifications section.
2
Temperature range: −40°C to +85°C.
3
See the Terminology section.
4
Guaranteed by design and characterization. Not production tested.
5
See the ADC Power vs. Throughput Rate section.