Datasheet
AD5590
Rev. A | Page 40 of 44
Table 26. ADC Shadow Register Bits
MSB LSB
DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
VIN0 VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 VIN7 VIN8 VIN9 VIN10 VIN11 VIN12 VIN13 VIN14 VIN15
07691-072
ASCLK
A
DOUT
ADIN
ASYNC
t
2
t
3
t
9
t
10
t
8
t
4
t
7
t
6
t
5
t
11
t
CONVERT
THREE-
STATE
THREE-
STATE
ADD3
FOUR IDENTIFICATION BITS
ADD2 ADD1 ADD0 DB11 DB10 DB2 DB1 DB0
C
12345613141516
V
IN
0V
IN
1V
IN
2V
IN
3V
IN
4V
IN
5V
IN
13 V
IN
14 V
IN
15
Figure 72. Writing to Shadow Register Timing Diagram