Datasheet
AD5590
Rev. A | Page 33 of 44
LDAC
Function
The outputs of all DACs can be updated simultaneously using
the hardware
LDAC
pin.
Synchronous
LDAC
: After new data is read, the DAC registers
are updated on the falling edge of the 32
nd
DSCLK pulse.
LDAC
can be permanently low or pulsed as in
Figure 4.
Asynchronous
LDAC
: The outputs are not updated at the same
time that the input registers are written to. When
LDAC
goes
low, the DAC registers are updated with the contents of the
input register.
Alternatively, the outputs of all DACs can be updated simulta-
neously using the software
LDAC
function by writing to Input
Register n and updating all DAC registers. Command 0011 is
reserved for this software
LDAC
function.
An
LDAC
register gives the user extra flexibility and control
over the hardware
LDAC
pin. This register allows the user to
select which combination of channels to simultaneously update
when the hardware
LDAC
pin is executed. Setting the
LDAC
bit
register to 0 for a DAC channel means that this channel’s update
is controlled by the
LDAC
pin. If this bit is set to 1, this channel
updates synchronously; that is, the DAC register is updated
after new data is read, regardless of the state of the
LDAC
pin.
It effectively registers the
LDAC
pin as being tied low. (See
Table 19 for the
LDAC
register mode of operation.) This
flexibility is useful in applications where the user wants to
simultaneously update select channels while the rest of the
channels are synchronously updating.
Writing to the DAC using Command 0110 loads the 8-bit
LDAC
register (DB7 to DB0). The default for each channel is
0, that is, the
LDAC
pin works normally. Setting the bits to 1
means the DAC channel is updated regardless of the state of
the
LDAC
pin. See Table 20 for the contents of the input shift
register during the
LDAC
register mode of operation.
Table 19.
LDAC
Register
LDAC
Bits (DB7 to DB0)
LDAC
Pin
LDAC
Operation
0 1/0 Determined by
LDAC
pin.
1 X—don’t care DAC channels update, overriding the
LDAC
pin. DAC channels see
LDAC
as 0.
Table 20. DAC 32-Bit Input Shift Register Contents for
LDAC
Register Function
MSB LSB
DB31
to DB28 DB27
DB26
DB25 DB24 DB23 DB22 DB21 DB20
DB19
to DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
X 0 1 1 0 X X X X X DAC H DAC G DAC F DAC E
DAC D DAC C DAC B
DAC A
Don’t
care
Command bits (C3 to C0) Address bits (A3 to A0)—
don’t care
Don’t
care
Setting
LDAC
bit to 1 overrides
LDAC
pin