Datasheet

AD5590
Rev. A | Page 10 of 44
DAC Timing Characteristics
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2. See Figure 4.
DACV
DD
= 4.5 V to 5.5 V. All specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 6.
Parameter
1
Limit at T
MIN
, T
MAX
; DACV
DD
= 2.7 V to 5.5 V Unit Conditions/Comments
t
1
2
20 ns min DSCLK cycle time
t
2
8 ns min DSCLK high time
t
3
8 ns min DSCLK low time
t
4
13 ns min
DSYNC
to DSCLK falling edge setup time
t
5
4 ns min Data setup time
t
6
4
ns min
Data hold time
t
7
0 ns min DSCLK falling edge to
DSYNC
rising edge
t
8
15 ns min Minimum
DSYNC
high time
t
9
13 ns min
DSYNC
rising edge to DSCLK fall ignore
t
10
0 ns min DSCLK falling edge to
DSYNC
fall ignore
t
11
10 ns min
LDAC
pulse width low
t
12
15 ns min DSCLK falling edge to
LDAC
rising edge
t
13
5 ns min
CLR
pulse width low
t
14
0 ns min DSCLK falling edge to
LDAC
falling edge
t
15
300 ns typ
CLR
pulse activation time
1
Sample tested at 25°C to ensure compliance.
2
Maximum DSCLK frequency is 50 MHz at V
DD
= 2.7 V to 5.5 V. Guaranteed by design and characterization; not production tested.
t
4
t
3
DSCLK
DSYNCx
DDIN
t
1
t
2
t
5
t
6
t
7
t
8
DB31
t
9
t
10
t
11
t
12
LDAC
1
LDAC
2
t
14
1
ASYNCHRONOUS LDAC UPDATE MODE.
2
SYNCHRONOUS LDAC UPDATE MODE.
CLR
t
13
t
15
VOUTx
DB0
07691-004
Figure 4. DAC Timing Characteristics