6 Input, 16 Output Analog I/O Port with Integrated Amplifiers AD5590 FEATURES Low input bias current: 1 pA maximum Single supply operation Low noise: 22 nV/√Hz Unity gain stable Flexible serial interface SPI-/QSPI-/MICROWIRE-/DSP-compatible −40°C to +85°C operation Available in 80-ball CSP_BGA package Input channels 12-bit successive approximation ADC 16 inputs with sequencer Fast throughput rate: 1 MSPS Wide input bandwidth: 70 dB SNR at fIN = 50 kHz Output channels 16 outputs with 12-bit DACs On-chip 2
AD5590 TABLE OF CONTENTS Features .............................................................................................. 1 DAC.............................................................................................. 14 Applications ....................................................................................... 1 ADC ............................................................................................. 18 Functional Block Diagram ...............................................
AD5590 GENERAL DESCRIPTION The AD5590 is a 16-channel input and 16-channel output analog I/O port with eight uncommitted amplifiers, operating from a single 4.5 V to 5.25 V supply. The AD5590 comprises 16 input channels multiplexed into a 1 MSPS, 12-bit successive approximation ADC with a sequencer to allow a preprogrammed selection of channels to be converted sequentially. The ADC contains a low noise, wide bandwidth track-and-hold amplifier that can handle input frequencies in excess of 1 MHz.
AD5590 SPECIFICATIONS ADC SPECIFICATIONS ADCVDD = VDRIVE = 2.7 V to 5.25 VREFA = 2.5 V, fSCLK 1 = 20 MHz, TA = TMIN to TMAX, unless otherwise noted. Table 1. Parameter DYNAMIC PERFORMANCE Signal-to-(Noise + Distortion) (SINAD) 3 Min Typ 68.5 70 70.5 70 70.5 −82 −82 −86 −80 dB dB dB dB dB dB dB dB −85 −85 10 50 −82 8.2 1.
AD5590 Parameter LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN1, 4 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating State Leakage Current Floating State Output Capacitance4 Output Coding Min Typ Unit 0.3 × VDRIVE +1 10 V V µA pF 0.7 × VDRIVE −1 VDRIVE − 0.2 800 300 300 1 ns ns ns MSPS 16 ASCLK cycles, ASCLK = 20 MHz Sine wave input Full-scale step input @ 5 V (see the Serial Interface section) 5.25 5.25 0.
AD5590 DAC SPECIFICATIONS DACVDD = 4.5 V to 5.25 V, RL = 2 kΩ to DACGND, CL = 200 pF to DACGND, VREFIN1 = VREFIN1 = DACVDD. All specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter STATIC PERFORMANCE 2 Resolution Integrated Nonlinearity (INL) Differential Nonlinearity (DNL) Zero-Code Error Zero-Code Error Drift3 Full-Scale Error Gain Error Gain Temperature Coefficient3 Offset Error DC Power Supply Rejection Ratio3 DC Crosstalk 3 External Reference Min Typ Max 12 −3 −0.25 ±0.5 +3 +0.
AD5590 Parameter POWER REQUIREMENTS DACVDD Min Typ Max Unit Conditions/Comments 1 5.5 V 2.6 4 3.2 5 mA mA All digital inputs at 0 or DACVDD, DAC active, excludes load current VIH = DACVDD = 4.5 V to 5.5 V, VIL = DACGND Internal reference off Internal reference on 0.8 2 µA VIH = DACVDD = 4.5 V to 5.5 V, VIL = DACGND 4.5 IDD (Normal Mode) 4 DACIDD (All Power-Down Modes) 5 DACVDD Temperature range is −40°C to +85°C, typical at 25°C.
AD5590 OPERATIONAL AMPLIFIER SPECIFICATIONS Electrical characteristics @ VSY = 5 V, VCM = VSY/2, TA = 25°C, unless otherwise noted. Table 4. Parameter INPUT CHARACTERISTICS Offset Voltage Symbol Typ Max Unit Conditions VOS 0.4 Offset Voltage Drift 1 Input Bias Current1 ∆VOS/∆T IB 1 0.2 IOS 0.1 Common-Mode Rejection Ratio CMRR 95 Large Signal Voltage Gain Input Capacitance1 AVO CDIFF CCM mV mV µV/°C pA pA pA pA dB dB V/mV pF pF −0.3 V < VCM < +5.3 V −40°C < TA < +85°C, −0.3 V < VCM < +5.
AD5590 TIMING SPECIFICATIONS ADC Timing Characteristics ADCVDD = 2.7 V to 5.25 V, VDRIVE ≤ ADCVDD, VREFA = 2.5 V; All specifications TMIN to TMAX, unless otherwise noted. Table 5. Parameter 1 fSCLK 2 Limit at TMIN, TMAX; ADCVDD = 5 V 10 20 16 × tASCLK 50 10 14 20 40 0.4 × tASCLK 0.
AD5590 DAC Timing Characteristics All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 4. DACVDD = 4.5 V to 5.5 V. All specifications TMIN to TMAX, unless otherwise noted. Table 6.
AD5590 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE TA = 25°C unless otherwise noted. VDD refers to DACVDD or ADCVDD. GND refers to DACGND or ADCGND. Table 7.
AD5590 12 11 VOUT14 VOUT10 10 9 VOUT8 DACGND VOUT1 8 7 LDAC DDIN 6 5 4 DSCLK DSYNC1 DACV DD 3 2 1 VOUT5 VOUT7 VOUT0 A VIN9 VIN8 OUT2 B VIN12 VIN10 OUT7 VOUT9 VOUT2 IN2(+) C IN7(–) VOUT11 VOUT4 IN2(–) D IN7(+) VOUT13 VOUT6 IN3(+) E IN6(+) VOUT15 VREFIN1 / VREFOUT1 IN3(–) F IN6(–) VREFIN2 / VREFOUT2 VIN5 OUT3 G V2– VIN15 V1– OUT1 H OUT6 VREFA VIN7 IN1(–) J OUT5 VIN14 VIN6 IN1(+) K IN5(–) VIN11 VIN13 V2+ IN5(+) IN4(+) IN4(–) OUT4 VOUT1
AD5590 Pin No. L7 Mnemonic ASCLK L6 VDRIVE A4, B8 DACVDD A9, B5 DACGND A8 LDAC A5 DSYNC1 B7 DSYNC2 B6 CLR A7 DDIN A6 DSCLK A1, B9, C2, B4, D2, A3, E2, A2 VOUT0 to VOUT7 A10, C11, A11, D11, B10, E11, A12, F11 VOUT8 to VOUT15 F2 VREFIN1/ VREFOUT1 G11 VREFIN2/ VREFOUT2 M3 V1+ H2 L9 V1− V2+ H12 M1, J1, D1, F1, M10, L12, G12, D12 M2, K1, C1, E1, M11, M12, F12, E12 L1, H1, B1, G1, M9, K12, J12, C12 V2− IN0(−) to IN7(−) IN0(+) to IN7(+) OUT0 to OUT7 Description Serial Clock.
AD5590 TYPICAL PERFORMANCE CHARACTERISTICS DAC DACVDD and ADCVDD = 5 V, VSY = 5 V, unless otherwise noted. 1.0 0.20 DACV DD = VREF = 5V 0.8 TA = 25°C DACVDD = 5V VREFOUT = 2.5V TA = 25°C 0.15 0.6 0.10 DNL ERROR (LSB) 0.2 0 –0.2 –0.4 0.05 0 –0.05 –0.10 –0.6 –0.15 –0.8 0 500 1000 1500 2000 2500 CODE 3000 3500 4000 –0.20 07691-006 –1.0 0 Figure 6. DAC INL, External Reference 500 1000 1500 2000 2500 CODE 3000 3500 4000 80 100 07691-009 INL ERROR (LSB) 0.4 Figure 9.
AD5590 0.50 DAC LOADED WITH FULL-SCALE SOURCING CURRENT 0.40 DAC LOADED WITH ZERO-SCALE SINKING CURRENT DACV DD = VREFA = 5V TA = 25°C 0.20 0.10 0 DACV DD –0.10 1 –0.20 MAX(C2)* 420.0mV DACV DD = 5V VREFOUT = 2.5V –0.30 2 –0.40 –6 –4 –2 0 2 CURRENT (mA) 4 6 8 10 CH1 2.0V Figure 12. DAC Headroom at Rails vs. Source and Sink CH2 500mV 5 1 DSCLK 3 3/4 SCALE 3 VOUT (V) DSYNC FULL SCALE 4 8.0ns/pt Figure 15. DAC Power-On Reset to 0 V 6 DACV DD = 5V VREFOUT = 2.
AD5590 2.5000 DACV DD = 5V VREFOUT = 2.5V TA = 25°C DAC LOADED WITH MIDSCALE 2.4995 2.4990 2.4980 10µV/DIV VOUT (V) 2.4985 2.4975 1 2.4970 2.4965 0 64 128 192 256 320 SAMPLE 384 448 512 5s/DIV Figure 20. 0.1 Hz to 10 Hz DAC Output Noise Plot, Internal Reference Figure 18. DAC Analog Crosstalk 800 2.4895 700 2.4890 600 OUTPUT NOISE (nV/√Hz) 2.4900 2.4880 2.4875 2.4870 2.4865 DACV DD = 5V VREFOUT = 2.5V TA = 25°C 4ns/SAMPLE NUMBER 2.
AD5590 5 –20 DACV DD = 5V TA = 25°C DAC LOADED WITH FULL SCALE VREF = 2V ±0.3V p-p –30 DACV DD = 5V TA = 25°C 0 –5 –40 –10 (dB) (dB) –50 –60 –15 –20 –70 –35 –100 2k 4k 6k FREQUENCY (Hz) 8k 10k 07691-022 –30 –90 Figure 22. DAC Total Harmonic Distortion VREFIN = DACVDD TA = 25°C 14 10 DACV DD = 5V 6 4 1 2 3 4 5 6 7 CAPACITANCE (nF) 8 9 10 07691-023 TIME (µs) 12 0 100k 1M FREQUENCY (Hz) Figure 24. DAC Multiplying Bandwidth 16 8 –40 10k Figure 23. DAC Settling Time vs.
AD5590 ADC DACVDD and ADCVDD = 5 V, VSY = 5 V, unless otherwise noted. –50 5 8192 POINT FFT fSAMPLE = 1MSPS fIN = 50kHZ SINAD = 70.697dB THD = –79.171dB SFDR = –79.93dB –15 –35 fS = 1MSPS TA = 25°C –55 ADCV DD = 5.25V RANGE = 0V TO REFIN RIN = 1000Ω –60 (dB) (dB) –65 –55 –70 RIN = 100Ω –75 –75 RIN = 5Ω –95 –80 50 100 150 200 250 300 350 400 450 500 FREQUENCY (kHz) 07691-025 0 100 1000 INPUT FREQUENCY (Hz) 07691-028 RIN = 10Ω –85 10 Figure 28. ADC THD vs.
AD5590 AMPLIFIER DACVDD and ADCVDD = 5 V, VSY = 5 V, unless otherwise noted. 400 1800 VSY = 5V 350 1400 INPUT BIAS CURRENT (pA) 1200 1000 800 600 400 300 250 200 150 100 50 200 0 25 1900 INPUT OFFSET VOLTAGE (µV) 50 AMPLIFIER SUPPLY CURRENT (µA) NUMBER OF AMPLIFIERS 100 150 125 Figure 34. Amplifier Input Bias Current vs. Temperature –40°C < TA < +125°C VCM = 2.5V 35 75 TEMPERATURE (°C) Figure 31.
AD5590 OUTPUT SATURATION VOLTAGE (mV) 40 120 VSY = 5V VSY = 5V TA = 25°C 100 30 VSY – VOH @ 1mA CMRR (dB) 80 20 VOL @ 1mA 60 40 10 –25 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) 0 100 07691-037 0 –40 120 VSY = ±2.5V TA = 25°C 300 100 VDD – VOH @ 10mA 250 PSRR (dB) 80 200 VOL @ 10mA 150 60 40 100 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) 0 100 ФM 45 10 0 0 –10 –20 1k VSY = ±2.
AD5590 50 0 VOUT (V) SMALL SIGNAL OVERSHOOT (%) VSY = 5V 45 TA = 25°C 40 35 VSY = ±2.5V AV = –50 –2.5 30 –OS 25 20 VIN (mV) 100 15 10 +OS 0 100 1000 LOAD CAPACITANCE (pF) TIME (20µs/DIV) 07691-043 0 10 07691-046 5 Figure 43. Small Signal Overshoot vs. Load Capacitance Figure 46. Amplifier Positive Overload Recovery VSY = 5V AV = 1 RL = 10kΩ CL = 200pF VSY = ±2.5V AV = –50 VOLTAGE (50mV/DIV) VOUT (V) 2.
AD5590 140 VSY = 5V VSY = 5V VOLTAGE NOISE (1µV/DIV) CHANNEL SEPARATION (dB) 120 100 80 60 40 TIME (1s/DIV) 0 100 1k 10k 100k FREQUENCY (Hz) Figure 51. Amplifier Channel Separation Figure 49. Amplifier 0.1 Hz to 10 Hz Input Voltage Noise 1000 100 10 1/F CORNER @ 100Hz 1 1 10 100 1000 FREQUENCY (Hz) 10000 07691-050 INPUT VOLTAGE NOISE (nV/√Hz) VSY = 5V TA = 25°C Figure 50. Amplifier Voltage Noise Density Rev.
AD5590 TERMINOLOGY DAC Integrated Nonlinearity For the DAC, relative accuracy, or integral nonlinearity (INL), is a measure of the maximum deviation in LSBs from a straight line passing through the endpoints of the DAC transfer function. DAC Differential Nonlinearity Differential nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity.
AD5590 Multiplying Bandwidth The amplifiers within the DAC have a finite bandwidth. The multiplying bandwidth is a measure of this. A sine wave on the reference (with full-scale code loaded to the DAC) appears on the output. The multiplying bandwidth is the frequency at which the output amplitude falls to 3 dB below the input. DAC Total Harmonic Distortion (THD) Total harmonic distortion is the difference between an ideal sine wave and its attenuated version using the DAC.
AD5590 ADC Peak Harmonic or Spurious Noise Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2 and excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it is a noise peak.
AD5590 THEORY OF OPERATION The AD5590 is an analog I/O module. The output port contains sixteen 12-bit voltage output DAC channels. The DAC channels are divided into two groups of eight DACs, each of which can be programmed independently. Each group of DACs contains its own internal 2.5 V reference. The references are powered down by default allowing the use of external references, if required. Either internal reference can be powered up and used as a reference for the ADC section.
AD5590 ADC SECTION CAPACITIVE DAC The ADC section is a fast, 16-channel, 12-bit, single-supply, analog-to-digital converter. The ADC is capable of throughput rates of up to 1 MSPS when provided with a 20 MHz clock. ADC CONVERTER OPERATION The ADC is a 12-bit successive approximation analog-to-digital converter based around a capacitive DAC. The ADC can convert analog input signals in the range 0 V to VREFA or 0 V to 2 × VREFA. Figure 54 and Figure 55 show simplified schematics of the ADC.
AD5590 ADC Transfer Function The output coding of the ADC is either straight binary or twos complement, depending on the status of the LSB (range bit) in the ADC control register. The designed code transitions occur midway between successive LSB values (that is, 1 LSB, 2 LSBs, and so on). The LSB size is equal to VREFA/4096. The ideal transfer characteristic for the ADC when straight binary coding is selected is shown in Figure 57. 111...111 111...
AD5590 An external reference source should be used to supply the 2.5 V reference to the ADC. Errors in the reference source results in gain errors in the ADC transfer function and adds to the specified full-scale errors of the ADC. A capacitor of at least 0.1 µF should be placed on the VREFA pin. Suitable reference sources for the ADC include the AD780, REF193, and the AD1852. If 2.5 V is applied to the VREFA pin, the analog input range can either be 0 V to 2.
AD5590 SERIAL INTERFACE The AD5590 contains independent serial interfaces for the ADC and DAC sections. The ADC uses the ASYNC, ASCLK, ADIN, and ADOUT pins. The VDRIVE pin allows the user to determine the output voltage of logic high signals. The DAC uses DSCLK, DDIN, DSYNC1, DSYNC2, LDAC, and CLR. of operation. At this stage, the DSYNCx line can be kept low or be brought high.
AD5590 In a normal write sequence, the DSYNCx line is kept low for 32 falling edges of DSCLK, and the DAC is updated on the 32nd falling edge and rising edge of DSYNCx. However, if DSYNCx is brought high before the 32nd falling edge, this acts as an interrupt to the write sequence. The shift register is reset, and the write sequence is seen as invalid. Neither an update of the DAC register contents nor a change in the operating mode occurs (see Figure 63).
AD5590 The bias generator of the selected DAC(s), output amplifier, resistor string, and other associated linear circuitry are shut down when the power-down mode is activated. The internal reference is powered down only when all channels are powered down. However, the contents of the DAC register are unaffected when in power-down. The time to exit power-down is typically 4 µs for DACVDD = 5 V. the user-configurable CLR register and sets the analog outputs accordingly.
AD5590 LDAC Function The outputs of all DACs can be updated simultaneously using the hardware LDAC pin. Synchronous LDAC: After new data is read, the DAC registers are updated on the falling edge of the 32nd DSCLK pulse. LDAC can be permanently low or pulsed as in Figure 4. Asynchronous LDAC: The outputs are not updated at the same time that the input registers are written to. When LDAC goes low, the DAC registers are updated with the contents of the input register.
AD5590 ACCESSING THE ADC BLOCK The ADC register can be accessed via the serial interface using the ASCLK , ADIN, ADOUT, and ASYNC pins. The VDRIVE pin can be used to dictate the logic levels of the output pins, allowing the ADC to be interfaced to a 3 V DSP while the ADC is operating at 5 V. ADC Modes of Operation The ADC has a number of different modes of operation. These modes are designed to provide flexible power management options.
AD5590 AutoShutdown (PM1 = 0, PM0 = 1) Autostandby (PM1 = PM0 = 0) In this mode, the ADC automatically enters shutdown at the end of each conversion when the ADC control register is updated. When the ADC is in shutdown, the track-and-hold is in hold mode. Figure 66 shows the general diagram of the operation of the ADC in this mode. In shutdown mode, all internal circuitry on the ADC is powered down. The ADC retains information in the ADC control register during shutdown.
AD5590 Powering Up the ADC Interfacing to the ADC When supplies are first applied to the ADC, the ADC can power up in any of the operating modes of the ADC. To ensure that the ADC is placed into the required operating mode, the user should perform a dummy cycle operation, as outlined in Figure 68. Figure 2 shows the detailed timing diagram for serial interfacing to the ADC.
AD5590 ADC Control Register time for the first ASCLK falling edge after the ASYNC falling edge. If the weak/TRI bit is set to 0 and the ADOUT line has been in true three-state between conversions, then depending on the particular DSP or microcontroller interfacing to the ADC, the ADD3 address bit may not be set up in time for the DSP/microcontroller to clock it in successfully.
AD5590 Table 23. ADC Channel Selection ADD3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 ADD2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ADD1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 ADD0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Analog Input Channel VIN0 VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 VIN7 VIN8 VIN9 VIN10 VIN11 VIN12 VIN13 VIN14 VIN15 Table 24. ADC Power Mode Selection PM1 1 PM0 1 1 0 0 1 0 0 Mode Normal operation. In this mode, the ADC remains in full power mode regardless of the status of any of the logic inputs.
AD5590 ADC Shadow Register POWER ON DUMMY CONVERSIONS ADIN = ALL 1s ASYNC ASYNC ADIN: WRITE TO CONTROL REGISTER, WRITE BIT = 1, SELECT CODING, RANGE, AND POWER MODE SELECT CHANNEL ADD3 TO CHANNEL ADD0 FOR CONVERSION, SEQ = 0 SHADOW = 1 ADOUT: CONVERSION RESULT FROM PREVIOUSLY SELECTED CHANNEL ADD3 TO CHANNEL ADD0 ADIN: WRITE TO SHADOW REGISTER, SELECTING WHICH CHANNELS TO CONVERT ON; CHANNELS SELECTED NEED NOT BE CONSECUTIVE WRITE BIT = 1, SEQ = 1, SHADOW = 0 WRITE BIT = 0 CONTINUOUSLY CONVERTS ON TH
AD5590 Table 26. ADC Shadow Register Bits MSB DB15 VIN0 DB14 VIN1 DB13 VIN2 DB12 VIN3 DB11 VIN4 DB10 VIN5 DB9 VIN6 DB8 VIN7 DB7 VIN8 DB6 VIN9 DB5 VIN10 DB4 VIN11 DB3 VIN12 DB2 VIN13 DB1 VIN14 LSB DB0 VIN15 C ASYNC t6 1 ASCLK 2 3 4 5 t4 t3 ADD2 ADOUT THREESTATE ADD3 ADIN tCONVERT t9 VIN0 VIN1 ADD1 13 14 t7 ADD0 DB11 FOUR IDENTIFICATION BITS VIN2 6 VIN3 15 t5 DB10 DB2 DB1 DB0 THREESTATE t8 t10 VIN4 16 t11 VIN5 VIN13 Figure 72.
AD5590 For example, if the ADC is operated in a continuous sampling mode with a throughput rate of 100 kSPS and an ASCLK of 20 MHz, with PM1 = 0 and PM0 = 1 (that is, the device is in autoshutdown mode), the power consumption is calculated as follows: the maximum power dissipation during normal operation is 12.5 mW. If the power-up time from autoshutdown is one dummy cycle, that is, 1 µs, and the remaining conversion time is another cycle, that is, 1 µs, the ADC dissipates 12.
AD5590 OUTLINE DIMENSIONS A1 CORNER INDEX AREA 10.00 BSC SQ BALL A1 PAD CORNER TOP VIEW 8.80 BSC SQ BOTTOM VIEW 0.80 BSC 0.60 REF 1.50 1.36 1.21 A B C D E F G H J K L M DETAIL A 0.65 REF 1.11 1.01 0.91 DETAIL A 0.36 REF 0.35 NOM 0.30 MIN *0.50 0.45 0.40 BALL DIAMETER 0.12 MAX COPLANARITY SEATING PLANE *COMPLIANT TO JEDEC STANDARDS MO-205-AC WITH THE EXCEPTION TO BALL DIAMETER. 011007-A 2.50 SQ 12 11 10 9 8 7 6 5 4 3 2 1 Figure 74.
AD5590 NOTES Rev.
AD5590 NOTES ©2008–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07691-0-7/11(A) Rev.
