Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - DA converter (DAC) PLCC 20

Summary of content (8 pages)

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AD558–SPECIFICATIONS (@ T = +258C, V A Model AD558J Typ Min = +5 V to +15 V unless otherwise noted) AD558K Typ Max Units 8 8 8 Bits RELATIVE ACCURACY 2 0°C to +70°C –55°C to +125°C ± 1/2 ± 1/4 ± 1/2 ± 3/4 ± 1/4 ± 3/8 LSB LSB 0 to +2.56 0 to +10 Max 0 to +2.56 0 to +10 +5 0.8 2.0 Max 0 to +2.56 0 to +10 +5 Internal Passive Pull-Down to Ground 1.5 3.0 0.8 2.0 Min 0 to +2.56 0 to +10 +5 Internal Passive Pull-Down to Ground 4 OUTPUT SETTLING TIME5 0 to 2.
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AD558 ABSOLUTE MAXIMUM RATINGS* 16 VOUT 1 (LSB) DB0 VCC to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to +18 V Digital Inputs (Pins 1–10) . . . . . . . . . . . . . . . . . . 0 V to +7.0 V VOUT . . . . . . . . . . . . . . . . . . . . . . . Indefinite Short to Ground Momentary Short to VCC Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 mW Storage Temperature Range N/P (Plastic) Packages . . . . . . . . . . . . . . . .
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AD558 CIRCUIT DESCRIPTION CHIP AVAILABILITY The AD558 consists of four major functional blocks, fabricated on a single monolithic chip (see Figure 2). The main D-to-A converter section uses eight equally-weighted laser-trimmed current sources switched into a silicon-chromium thin-film R/2R resistor ladder network to give a direct but unbuffered 0 mV to 400 mV output range.
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Applications–AD558 The only consideration in selecting a supply voltage is that, in order to be able to use the 0 V to 10 V output range, the power supply voltage must be between +11.4 V and +16.5 V. If, however, the 0 V to 2.56 V range is to be used, power consumption will be minimized by utilizing the lowest available supply voltage (above +4.5 V).
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AD558 tDH DATA INPUTS 2.0V tDS 0.8V VOUT 16 AD558 VOUT SENSE 15 RL 2.0V CS OR CE 0.8V RP-D = 2x VEE NEGATIVE SUPPLY tW 1/2 LSB DAC V OUTPUT tSETTLING tW = STORAGE PULSE WIDTH = 200ns MIN tDH = DATA HOLD TIME = 10ns MIN tDS = DATA SETUP TIME = 200ns MIN tSETTLING = DAC OUTPUT SETTLING TIME TO ±1/2 LSB VEE (in kΩ) Figure 9. Improved Settling Time available, bipolar output ranges may be achieved by suitable output offsetting and scaling. Figure 10 shows how a ± 1.
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AD558 OUTPUT AMP ADDRESS BUS 16 0.5mA VOUT 16 16 –V 15 VOUT SENSE 14 VOUT SELECT ADDRESS SELECT PULSE LOGIC 8080A CS MEMW 13 AD558 VOUT CE AGND DB0–DB7 b. 0 V to 10 V Output Range Figure 11. Offset Connection Diagrams 8 8 DATA BUS INTERFACING THE AD558 TO MICROPROCESSOR DATA BUSES MEMW → CE DECODED ADDRESS SELECT PULSE → CS The AD558 is configured to act like a “write only” location in memory that may be made to coincide with a read only memory location or with a RAM location.
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AD558 mA OUTLINE DIMENSIONS 16 Dimensions shown in inches and (mm). 14 N (Plastic) Package ICC C558f–21–8/87 12 10 4 6 8 10 12 14 16 18 VOLTS VCC Figure 15. Quiescent Current vs. Power Supply Voltage for AD558 D (Ceramic) Package Figure 16. AD558 Settling Characteristics Detail 0 V to 2.56 V Output Range Full-Scale Step P (PLCC) Package PRINTED IN U.S.A. Figure 17. AD558 Settling Characteristic Detail 0 V to 10 V Output Range Full-Scale Step Figure 18. AD558 Logic Timing –8– REV.