Datasheet

REV. A
AD5582/AD5583
–17–
compliance is mainly limited by the op amp supply voltages.
This circuit can be used in 4 to 20 mA current transmitters with
up to 500 W of load.
U4
AD8510
–
+
R3'
50
R3
50
C1
10pF
R2
15k
R2'
15k
R1'
150k
VL
IL
LOAD
R1
150k
U2
AD5582
V
REFH
R1
RCT
R2
V
REFL
OP1177
–
+
+5V
V
DD
V
SS
U1
ADR421
+2.5V
–2.5V
DECOUPLING CAPS ARE OMITTED FOR CLARITY
–5V
+5V
+5V
–5V
+15V
–15V
V
DAC
Figure 6. Programmable Current Source with Bidirectional
Current Control and High Voltage Compliance Capabilities
Figure 6 shows that if the resistor network is matched, the load
current is:
I
RRR
R
V
L DAC
=
+
()
231
3
/
(4)
R3 in theory can be made small to achieve the current needed
within the U4 output current driving capability. In this circuit,
the AD8510 can deliver ± 20 mA in both directions and the
voltage compliance approaches ± 15 V.
This circuit is versatile, but users must pay attention to the
compensation. Without C1, it can be shown that the output
impedance becomes:
Z
RR R R
RR R R R R
O
=
+
()
+
()
+
()
131 2
12 3 1 2 3
'
''–'
(5)
If the resistors are perfectly matched, Z
O
is infinite, which is
highly desirable. On the other hand, if they are not matched, Z
O
can either be positive or negative. The latter, because of the
pole in the right S-plane, can cause oscillation. As a result, C1
in the range of a few pF is needed to prevent the oscillation. For
critical applications, C1 should be found empirically without
overcompensating.
Boosted Programmable Voltage Source
For users who need higher than 20 mA current driving capabil-
ity, they can add an external op amp and power transistors. The
capacitive loading capability will change, but it can still drive
100 nF capacitive load without oscillation in this circuit. Figure 7
shows a programmable power supply with 200 mA capability.
U3
OP1177
–
+
U1
REF198
V
DD
C1
1F
+4.096V
+5V
U2
AD5582
V
REFH
V
REFL
V
DD
V
SS
+15V
FDV30IN
N1
LOAD
V
O
DECOUPLING CAPS ARE OMITTED FOR CLARITY
Figure 7. Boosted Programmable Voltage Source
Table I. AD5582/AD5583 Logic Table
INPUT DAC OPERATION SELECTED
A1 A0 R/WCS LDAC RS REGISTER REGISTER MODE DAC
000001Write Transparent Transparent A
010001Write Transparent Transparent B
100001Write Transparent Transparent C
110001Write Transparent Transparent D
000011Write Hold Write Input A
010011Write Hold Write Input B
100011Write Hold Write Input C
110011Write Hold Write Input D
001011Read Hold Readback to D0 to DN A
011011Read Hold Readback to D0 to DN B
101011Read Hold Readback to D0 to DN C
111011Read Hold Readback to D0 to DN D
XXX101Hold Update All Registers Update All Registers All
XXX 1 1 1 Hold Hold Hold All
XXXXX0All registers reset to midscale or zero scale. All
XXX 1 X ≠ All registers latched to midscale or zero scale. All
MSB = 0 resets to zero scale, MSB = 1 resets to midscale. X: Don’t Care. Input and output registers are transparent when asserted.