Datasheet

AD5570
Rev. C | Page 6 of 24
TIMING CHARACTERISTICS
DAISY-CHAINING AND READBACK
V
DD
= +12 V ± 5%, V
SS
= −12 V ± 5% or V
DD
= +15 V ± 10%, V
SS
= −15 V ± 10%, V
REF
= 5 V, REFGND = AGND = DGND = 0 V, R
L
= 5 kΩ,
C
L
= 200 pF to AGND; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 3.
Parameter
1, 2
Limit at T
MIN
, T
MAX
Unit Description
f
MAX
2 MHz max SCLK frequency
t
1
500 ns min SCLK cycle time
t
2
200 ns min SCLK high time
t
3
200 ns min SCLK low time
t
4
10 ns min
SYNC
to SCLK falling edge setup time
t
5
35 ns min Data setup time
t
6
0 ns min Data hold time
t
7
45 ns min
SCLK falling edge to SYNC
rising edge
t
8
45 ns min
Minimum SYNC
high time
t
9
0 ns min
SYNC
rising edge to LDAC falling edge
t
10
50 ns min
LDAC
pulse width
t
14
3
200 ns max Data delay on SDO
1
All parameters guaranteed by design and characterization. Not production tested.
2
All input signals are measured with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+V
IH
)/2. SDO; R
PULLUP
= 5 kΩ, C
L
= 15 pF.
3
With C
L
= 0 pF, t
14
= 100 ns.
SCLK
SYNC
SDIN
DB15 (N)
DB15 (N)
DB0 (N)
DB0 (N)
DB15
(N + 1)
DB15
(N + 1)
DB0
(N + 1)
LDAC
1
SDO
LDAC
2
NOTES
1
ASYNCHRONOUS LDAC UPDATE MODE.
2
SYNCHRONOUS LDAC UPDATE MODE.
t
1
t
8
t
10
t
2
t
3
t
4
t
6
t
5
t
9
t
7
t
14
03760-003
Figure 3. Daisy-Chaining Timing Diagram