Datasheet

AD5570
Rev. C | Page 5 of 24
TIMING CHARACTERISTICS
STANDALONE
V
DD
= +12 V ± 5%, V
SS
= −12 V ± 5% or V
DD
= +15 V ± 10%, V
SS
= −15 V ± 10%, V
REF
= 5 V, REFGND = AGND = DGND = 0 V, R
L
= 5 kΩ,
C
L
= 200 pF to AGND; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter
1, 2
Limit at T
MIN
, T
MAX
Unit Description
f
MAX
10 MHz max SCLK frequency
t
1
100 ns min SCLK cycle time
t
2
35 ns min SCLK high time
t
3
35 ns min SCLK low time
t
4
10 ns min
SYNC
to SCLK falling edge setup time
t
5
35 ns min Data setup time
t
6
0 ns min Data hold time
t
7
45 ns min
SCLK falling edge to SYNC
rising edge
t
8
45 ns min
Minimum SYNC
high time
t
9
0 ns min
SYNC
rising edge to LDAC falling edge
t
10
50 ns min
LDAC
pulse width
t
11
0 ns min
LDAC
falling edge to SYNC falling edge (no update)
t
12
0 ns min
LDAC
rising edge to SYNC rising edge (no update)
t
13
20 ns min
CLR
pulse width
1
All parameters guaranteed by design and characterization. Not production tested.
2
All input signals are measured with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+V
IH
)/2.
DB15
DB0
SCLK
SYNC
SDIN
LDAC
1
CLR
LDAC
2
NOTES
1
ASYNCHRONOUS LDAC UPDATE MODE. UPDATE ON FALLING EDGE OF LDAC.
2
SYNCHRONOUS LDAC UPDATE MODE. UPDATE ON RISING EDGE OF SYNC.
t
3
t
2
t
5
t
6
t
7
t
9
t
1
t
4
t
8
t
12
t
11
t
10
t
13
03760-002
Figure 2. Serial Interface Timing Diagram