Datasheet

AD5570
Rev. C | Page 14 of 24
TEMPERATURE (°C)
OFFSET ERROR (LSB)
–40
–10
–9
–8
–7
–6
–5
–4
0
–1
–3
–2
100806040200–20 120
03760-031
V
DD
/V
SS
= ±12V OR ±15V
REFIN = 5V
Figure 24. Offset Error vs. Temperature
TEMPERATURE (°C)
BIPOLAR ZERO ERROR (LSB)
–40
–10
–9
–8
–7
–6
–5
–4
0
–1
–3
–2
100806040200–20 120
V
DD
/V
SS
= ±12V
V
DD
/V
SS
= ±15V
REFIN = +5V
03760-032
Figure 25. Bipolar Zero Error vs. Temperature
TEMPERATURE (°C)
GAIN ERROR (LSB)
–40
–10
–8
–6
–4
–2
0
2
10
8
4
6
100806040200–20 120
V
DD
/V
SS
= ±12V
V
DD
/V
SS
= ±15V
REFIN = +5V
03760-034
Figure 26. Gain Error vs. Temperature
V
LOGIC
(V)
I
DD
(mA)
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
3.75
3.80
3.85
3.90
3.95
4.00
4.05
4.10
4.15
5.0
03760-035
T
A
= 25°C
REFIN = 5V
15V SUPPLIES
DECREASING
INCREASING
12V SUPPLIES
INCREASING
DECREASING
Figure 27. Supply Current vs. Logic Input Current for SCLK,
SYNC
, SDIN,
and
LDAC
Increasing and Decreasing
–10
–4
–6
–8
4
2
0
–2
11
10
8
6
1µs/DIV
V
DD
= +15V
V
SS
= –15V
REFIN = +5V
T
A
= 25°C
03760-046
TIME (µs)
V
OUT
(V)
Figure 28. Settling Time
CAPACITANCE (nF)
TIME (µs)
0123456789
0
5
10
15
20
25
30
35
40
9.4
T
A
= 25°C
REFIN = +5V
V
DD
/V
SS
= ±12V
V
DD
/V
SS
= ±15V
03760-037
Figure 29.14-Bit Settling Time vs. Load Capacitance