Datasheet
AD5544/AD5554 Data Sheet
Rev. G | Page 8 of 24
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AD5544/
AD5554
TOP VIEW
(Not to Scale)
A
GND
A
A
GND
D
I
OUT
A
I
OUT
D
V
REF
A
V
REF
D
R
FB
AR
FB
D
MSB DGND
V
SS
V
DD
A
GND
F
CLK SDO
SDI NC
R
FB
B
R
FB
C
V
REF
B
V
REF
C
I
OUT
B
I
OUT
C
A
GND
BA
GND
C
NC = NO CONNECT
LDAC
CS
RS
00943-003
Figure 5. TSSOP Pin Configuration
NOTES
1. NC = NO CONNE
C
T.
2
. CONNECT EXPOSED PAD TO AGND.
24
DGND
23
V
SS
22
A
GND
F
21
LDAC
20
SDO
19
NC
18
R
FB
C
17
V
REF
C
1
2
3
4
5
6
7
8
A
GND
A
I
OUT
A
V
REF
A
R
FB
A
MSB
RS
V
DD
CS
9
10
11
12
13
14
15
16
CLK
SDI
R
FB
B
V
REF
B
I
OUT
B
A
GND
B
A
GND
C
I
OUT
C
32
31
30
29
28
27
26
25
NC
NC
NC
NC
A
GND
D
I
OUT
D
V
REF
D
R
FB
D
AD5544
TOP VIEW
(Not to Scale)
00943-035
Figure 6. LFCSP Pin Configuration
Table 4. Pin Function Descriptions
TSSOP
Pin No.
LFCSP
Pin No. Mnemonic Description
1 1 A
GND
A DAC A Analog Ground.
2 2 I
OUT
A DAC A Current Output.
3 3 V
REF
A
DAC A Reference Voltage Input Terminal. Establishes DAC A full-scale output voltage. This pin can be
tied to the V
DD
pin.
4 4 R
FB
A Establish the voltage output for DAC A by connecting to an external amplifier output.
5 5 MSB
MSB Bit. Set pin during a reset pulse (RS
) or at system power-on if tied to ground or V
DD
.
6 6
RS
Reset Pin, Active Low Input. Input registers and DAC registers are set to all 0s or half-scale code
(0x8000 for the AD5544 and 0x2000 for the AD5554), determined by the voltage on the MSB pin.
Register data = 0x0000 when MSB = 0.
7 7 V
DD
Positive Power Supply Input. Specified range of operation: 5 V ± 10%.
8 8
CS
Chip Select, Active Low Input. Disables shift register loading when high. Transfers serial register data
to the input register when CS
/LDAC returns high. Does not affect LDAC operation.
9 9 CLK Clock Input. Positive edge clocks data into the shift register.
10 10 SDI Serial Data Input. Input data loads directly into the shift register.
11 11 R
FB
B Establish the voltage output for DAC B by connecting to an external amplifier output.
12 12 V
REF
B
DAC B Reference Voltage Input Terminal. Establishes DAC B full-scale output voltage. This pin can be
tied to the V
DD
pin.
13 13 I
OUT
B DAC B Current Output.
14 14 A
GND
B DAC B Analog Ground.
15 15 A
GND
C DAC C Analog Ground.
16 16 I
OUT
C DAC C Current Output.
17 17 V
REF
C
DAC C Reference Voltage Input Terminal. Establishes DAC C full-scale output voltage. This pin can be
tied to the V
DD
pin.
18 18 R
FB
C Establish the voltage output for DAC C by connecting to an external amplifier output.
19 19 NC No Connect. Leave the pin unconnected.
20 20 SDO
Serial Data Output. Input data loads directly into the shift register. Data appears at SDO at 19 clock
pulses for the AD5544 and 17 clock pulses for the AD5554 after input at the SDI pin.
21 21
LDAC
Load DAC Register Strobe, Level Sensitive Active Low. Transfers all input register data to DAC
registers. Asynchronous active low input. See Table 8 and Table 9 for operation.
22 22 A
GND
F High Current Analog Force Ground.
23 23 V
SS
Negative Bias Power Supply Input. Specified range of operation: −5.5 V to +0.3 V.
24 24 DGND Digital Ground Pin.
25 25 R
FB
D Establish the voltage output for DAC D by connecting to an external amplifier output.