Datasheet

Data Sheet AD5544/AD5554
Rev. G | Page 17 of 24
INPUT
REGISTER
R
INPUT
REGISTER
R
INPUT
REGISTER
R
INPUT
REGISTER
R
DAC A
B
C
D
2:4
DECODE
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
A0
A1
EN
16
DAC D
REGISTER
R
DAC C
REGISTER
R
DAC B
REGISTER
R
DAC A
REGISTER
R
POWER-
ON
RESET
DAC B
DAC C
DAC D
DAC A
AD5544
V
REF
A B C D
V
DD
R
FB
A
I
OUT
A
A
GND
A
R
FB
B
I
OUT
B
A
GND
B
R
FB
C
I
OUT
C
A
GND
C
R
FB
D
I
OUT
D
A
GND
D
A
GND
F
DGND MSB V
SS
SET
MSB
SET
MSB
SDO
SDI
CLK
CS
RS
LDAC
00943-029
Figure 23. System Level Digital Interfacing
EN
SHIFT REGISTER
ADDRESS
DECODER
A
B
C
D
TO INPUT REGISTER
19
TH
/17
TH
CLOCK
SDO
SDI
CLK
CS
00943-030
Figure 24. AD5544/AD5554 Equivalent Logic Interface
POWER-ON RESET
When the V
DD
power supply is turned on, an internal reset strobe
forces all the input and DAC registers to the zero-code state or
half-scale state, depending on the MSB pin voltage. The V
DD
power
supply should have a smooth positive ramp without drooping to
have consistent results, especially in the region of V
DD
= 1.5 V to
2.3 V. The V
SS
supply has no effect on the power-on reset perform-
ance. The DAC register data stays at a zero-scale or half-scale
setting until a valid serial register data load takes place.
ESD PROTECTION CIRCUITS
All logic input pins contain back-biased ESD protection Zener
diodes that are connected to ground (DGND) and V
DD
, as
shown in Figure 25.
V
DD
DIGITAL
INPUTS
5kΩ
DGND
00943-031
Figure 25. Equivalent ESD Production Circuits
POWER SUPPLY SEQUENCE
As standard practice, it is recommended that V
DD
, V
SS
, and ground
be powered up prior to any reference. The ideal power-up sequence
is as follows: A
GND
x, DGND, V
DD
, V
SS
, V
REF
x, and the digital inputs.
A noncompliance power-up sequence may elevate the reference
current, but the devices resume normal operation once V
DD
and
V
SS
are powered up.