Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - DA converter (DAC) SSOP 28

Quad, Current-Output,

Serial-Input 16-/14-Bit DACs

Data Sheet

AD5544/AD5554

Rev. G Document Feedback

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FEATURES

AD5544: 16-bit resolution

INL of ±1 LSB (B Grade)

AD5554: 14-bit resolution

INL of ±0.5 LSB (B Grade)

2 mA full-scale current ± 20%, with V

REF

= ±10 V

0.9 µs settling time to ±0.1%

12 MHz multiplying bandwidth

Midscale glitch of −1 nV-sec

Midscale or zero-scale reset

4 separate, 4-quadrant multiplying reference inputs

SPI-compatible, 3-wire interface

Double-buffered registers enable

Simultaneous multichannel change

Internal power-on reset

Temperature range: −40°C to +125°C

Compact 28-lead SSOP and 32-lead LFCSP

APPLICATIONS

Automatic test equipment

Instrumentation

Digitally controlled calibration

FUNCTIONAL BLOCK DIAGRAM

INPUT

DAC A

2:4

DECODE

DAC A

POWER-ON

RESET

D10

D11

D12

D13

D14

D15

OUT

GND

LDAC

MSB

DGND

CLK

SDI

SDO

REF

A B C

OUT

GND

OUT

GND

OUT

GND

AD5544

INPUT

DAC B

DAC C

DAC D

DAC A

DAC B

DAC D

DAC C

00943-001

Figure 1.

GENERAL DESCRIPTION

The AD5544/AD5554 quad, 16-/14-bit, current output, digital-

to-analog converters (DACs) are designed to operate from a

2.7 V to 5.5 V supply range.

The applied external reference input voltage (V

REF

x) determines

the full-scale output current. Integrated feedback resistors (R

)

provide temperature-tracking, full-scale voltage outputs when

combined with an external I-to-V precision amplifier.

A double-buffered serial data interface offers high speed, 3-wire,

SPI- and microcontroller-compatible inputs using serial data in

(SDI), a chip select (

), and clock (CLK) signals. In addition,

a serial data out pin (SDO) allows for daisy-chaining when multiple

packages are used. A common, level-sensitive, load DAC strobe

(

LDAC

) input allows the simultaneous update of all DAC outputs

from previously loaded input registers. Additionally, an internal

power-on reset forces the output voltage to 0 at system turn-on.

The MSB pin allows system reset assertion (

) to force all registers

to zero code when MSB = 0 or to half-scale code when MSB = 1.

The AD5544 is packaged in the compact 28-lead SSOP and 32-

lead LFCSP. The AD5554 is packed in the compact 28-lead SSOP.

The EV-AD5544/45SDZ is available for evaluating DAC perfor-

mance. For more information, see the UG-285 evaluation board

user guide.

0.7

0.6

0.5

0.4

0.3

0.2

0.1

–0.1

–0.2

0 10,000 30,000

50,000 70,000

00943-002

INL ERROR (LSB)

CODE

20,000 40,000 60,000

Figure 2. AD5544 INL vs. Code Plot (T

= 25°C)

Summary of content (24 pages)

PAGE 1
Quad, Current-Output, Serial-Input 16-/14-Bit DACs AD5544/AD5554 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM VREFA B C D VDD D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 A0 A1 SDI SDO RFBA INPUT REGISTER R DAC A REGISTER R DAC A IOUTA AGNDA RFBB 16 INPUT REGISTER R DAC B REGISTER R DAC B IOUTB AGNDB RFBC INPUT REGISTER R DAC C REGISTER R DAC C IOUTC AGNDC CS RFBD EN CLK INPUT REGISTER R DAC A B C D 2:4 DECODE APPLICATIONS DAC D REGISTER R DAC D IOUTD AGNDD AD5544 POWER
PAGE 2
AD5544/AD5554 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Digital-to-Analog Converter (DAC) ....................................... 13 Applications ....................................................................................... 1 Serial Data Interface ....................................................................... 15 Functional Block Diagram .......................................................
PAGE 3
Data Sheet AD5544/AD5554 SPECIFICATIONS AD5544 ELECTRICAL CHARACTERISTICS VDD = 2.7 V to 5.5 V, VSS = 0 V, IOUTx = virtual GND, AGNDx = 0 V, VREFA = VREFB = VREFC = VREFD = 10 V, TA = full operating temperature range of −40°C to +125°C, unless otherwise noted. Table 1.
PAGE 4
AD5544/AD5554 Parameter Power Dissipation Power Supply Sensitivity AC CHARACTERISTICS 4 Output Voltage Settling Time Reference Multiplying Bandwidth (BW) DAC Glitch Impulse Feedthrough Error Crosstalk Error Digital Feedthrough Total Harmonic Distortion Output Spot Noise Voltage Data Sheet Symbol PDISS PSS Test Condition/Comments Logic inputs = 0 V ∆VDD = ±5% tS BW − 3 dB To ±0.1% of full scale, data = 0x0000 to 0xFFFF to 0x0000 VREFx = 5 V p-p, data = 0xFFFF, CFB = 2.0 pF, 0.
PAGE 5
Data Sheet Parameter Clock to SDO Propagation Delay Load DAC Pulse Width Data Setup Data Hold Load Setup Load Hold SUPPLY CHARACTERISTICS Power Supply Range Positive Supply Current Negative Supply Current Power Dissipation Power Supply Sensitivity AC CHARACTERISTICS 4 Output Voltage Settling Time Reference Multiplying Bandwidth (BW) DAC Glitch Impulse Feedthrough Error Crosstalk Error Digital Feedthrough Total Harmonic Distortion Output Spot Noise Voltage AD5544/AD5554 Symbol tPD Test Condition/Comments
PAGE 6
AD5544/AD5554 Data Sheet TIMING DIAGRAMS SDI A1 A0 D15 D14 D13 D12 D11 D10 D1 D0 INPUT REG LD CLK tDS tCSS CS tDH tCH tCL tCSH tLDS LDAC tLDH tLDAC 00943-004 tPD SDO Figure 3. AD5544 Timing Diagram A1 A0 D13 D12 D11 D10 D09 D08 D1 D0 INPUT REG LD CLK CS tCSS tDS tDH tCH tCL tCSH tLDS LDAC tPD SDO Figure 4. AD5554 Timing Diagram Rev.
PAGE 7
Data Sheet AD5544/AD5554 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter VDD to GND VSS to GND VREFx to GND Logic Input and Output to GND V(IOUTx) to GND AGNDx to DGND Input Current to Any Pin Except Supplies Package Power Dissipation Thermal Resistance 28-Lead SSOP 32-Lead LFCSP Maximum Junction Temperature (TJ Max) Operating Temperature Range Storage Temperature Range Lead Temperature Vapor Phase, 60 Sec Infrared, 15 Sec Rating −0.3 V, +8 V +0.3 V, −7 V −18 V, +18 V −0.3 V, +8 V −0.3 V, VDD + 0.3 V −0.
PAGE 8
AD5544/AD5554 Data Sheet 27 I OUTD VREF A 3 26 V REF D RFBA 4 25 RFBD MSB 5 24 DGND RS 6 AD5544/ AD5554 VDD 7 1 2 3 4 5 6 7 CS 8 AGNDA IOUTA VREF A RFBA MSB RS VDD 23 VSS 22 AGNDF TOP VIEW 21 LDAC (Not to Scale) 20 SDO 18 R C FB VREF B 12 17 V REF C IOUTB 13 16 I OUTC AGNDB 14 15 AGNDC NC = NO CONNECT DGND VSS AGNDF LDAC SDO NC RFBC VREF C 9 10 11 12 13 14 15 16 19 NC AD5544 TOP VIEW (Not to Scale) 24 23 22 21 20 19 18 17 CLK SDI RFBB VREF B IOUTB AGNDB AGNDC IOUTC SDI 10 RFBB
PAGE 9
Data Sheet AD5544/AD5554 TSSOP Pin No. 26 LFCSP Pin No. 26 Mnemonic VREFD 27 28 N/A N/A N/A N/A N/A 27 28 29 30 31 32 33 IOUTD AGNDD NC NC NC NC EPAD Description DAC D Reference Voltage Input Terminal. Establishes DAC D full-scale output voltage. This pin can be tied to the VDD pin. DAC D Current Output. DAC D Analog Ground. Do not connect. Do not connect. Do not connect. Do not connect. Connect the exposed pad to AGNDx. Rev.
PAGE 10
AD5544/AD5554 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 1.5 0.10 1.0 0xF000 –0.05 0.5 –0.10 INL (LSB) –0.15 –0.20 0x7FFF 0x8000 0 –0.5 –0.25 –0.30 –0.40 0 10,000 20,000 30,000 40,000 CODE 50,000 60,000 –1.5 –2000 70,000 0.15 0.75 0.10 0.50 0.05 0.25 DNL (LSB) 1.00 0 –0.50 –0.15 –0.75 00943-007 –0.10 6000 500 1000 1500 2000 –1.00 –1000 8000 10,000 12,000 14,000 16,000 18,000 CODE VDD = 5V VREF = 10V 0x0FFF –0.25 4000 0 0 –0.05 2000 –500 Figure 10.
PAGE 11
Data Sheet AD5544/AD5554 10,000 –3.88 –3.90 –3.92 1000 –3.96 IDD (µA) VOUT (V) –3.94 –3.98 –4.00 ZERO SCALE MIDSCALE FULL SCALE 0x5555 100 –4.02 10 –4.04 1 1k 0.4 0.5 0.6 0.7 0.8 0.9 TIME (µs) 1.0 1.2 1.1 00943–012 –4.08 Figure 13. AD5544 Midscale Transition 10k 100k 1M CLOCK FREQUENCY (Hz) 10M 100M 00943-015 –4.06 Figure 16. AD5544 Power Supply Current vs.
PAGE 12
AD5544/AD5554 Data Sheet 300 SUPPLY CURRENT (µA) 250 200 150 100 0 0 0.5 1.0 1.5 2.0 2.5 3.0 LOGIC INPUT (V) 3.5 4.0 4.5 5.0 00943-017 50 Figure 19. AD5544/AD5554 Power Supply Current vs. Logic Input Voltage Rev.
PAGE 13
Data Sheet AD5544/AD5554 THEORY OF OPERATION DIGITAL-TO-ANALOG CONVERTER (DAC) Each part contains four current-steering R-R ladder DACs. Figure 20 shows a typical equivalent DAC. Each DAC contains a matching feedback resistor for use with an external I-to-V converter amplifier. The RFBx pin connects to the output of the external amplifier. The IOUTx terminal connects to the inverting input of the external amplifier.
PAGE 14
AD5544/AD5554 Data Sheet 15V 2R 5V + ANALOG POWER SUPPLY R VDD AD5544 RR VREF X 2R RFBX R 2R 2R R 5kΩ 15V S2 S1 VCC IOUTX AGNDF AGNDX VOUT A1 + VEE FROM OTHER DACS AGND LOAD DIGITAL INTERFACE CONNECTIONS OMITTED. FOR CLARITY SWITCHES S1 AND S2 ARE CLOSED, AND VDD MUST BE POWERED. Figure 22. Recommended Kelvin-Sensed Hookup Rev.
PAGE 15
Data Sheet AD5544/AD5554 SERIAL DATA INTERFACE Similarly, two right-justified data bytes can be written to the AD5554. Keeping the CS line low between the first and second byte transfer results in a successful serial register update. The AD5544/AD5554 use a 3-wire (CS, SDI, CLK), SPI-compatible serial data interface. Serial data of the AD5544/AD5554 is clocked into the serial input register in an 18-bit and 16-bit data-word format, respectively. The MSB bits are loaded first.
PAGE 16
AD5544/AD5554 Data Sheet TRUTH TABLES Table 8.
PAGE 17
Data Sheet AD5544/AD5554 VREF A B C D CS EN AD5544 VDD CLK SDI SDO D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 A0 A1 RFBA 16 INPUT REGISTER R DAC A REGISTER R DAC A IOUTA AGNDA RFBB INPUT REGISTER R DAC B REGISTER R DAC B IOUTB AGNDB DAC A B C D 2:4 DECODE RFBC INPUT REGISTER R DAC C REGISTER R DAC C IOUTC AGNDC RFBD INPUT REGISTER R DAC D REGISTER R DAC D IOUTD AGNDD SET MSB SET MSB DGND MSB LDAC 00943-029 AGNDF POWERON RESET VSS RS Figure 23.
PAGE 18
AD5544/AD5554 Data Sheet AD5544/AD5554 LAYOUT AND POWER SUPPLY BYPASSING VDD It is good practice to employ a compact, minimum lead length layout design. The leads to the input should be as direct as possible with a minimum conductor length. Ground paths should have low resistance and low inductance. C4 10µF VSS + C1 0.1µF C2 0.1µF VDD AGNDX VSS DGND 00943-032 Similarly, it is good practice to bypass the power supplies with quality capacitors for optimum stability.
PAGE 19
Data Sheet AD5544/AD5554 APPLICATIONS INFORMATION REFERENCE SELECTION The AD5544/AD5554 are, inherently, two-quadrant multiplying DACs. That is, they can be easily set up for unipolar output operation. The full-scale output polarity is the inverse of the reference input voltage. In some applications, it may be necessary to generate the full four-quadrant multiplying capability or a bipolar output swing.
PAGE 20
AD5544/AD5554 Data Sheet Table 10. Suitable Analog Devices Precision References Part No. ADR01 ADR01 ADR02 ADR02 ADR03 ADR03 ADR06 ADR06 ADR420 ADR421 ADR423 ADR425 ADR431 ADR435 ADR391 ADR395 Output Voltage (V) 10 10 5.0 5.0 2.5 2.5 3.0 3.0 2.048 2.50 3.00 5.00 2.500 5.000 2.5 5.0 Initial Tolerance (%) 0.05 0.05 0.06 0.06 0.1 0.1 0.1 0.1 0.05 0.04 0.04 0.04 0.04 0.04 0.16 0.10 Maximum Temperature Drift (ppm/°C) 3 9 3 9 3 9 3 9 3 3 3 3 3 3 9 9 ISS (mA) 1 1 1 1 1 1 1 1 0.5 0.5 0.5 0.5 0.8 0.8 0.12 0.
PAGE 21
Data Sheet AD5544/AD5554 OUTLINE DIMENSIONS 10.50 10.20 9.90 15 28 5.60 5.30 5.00 1 8.20 7.80 7.40 14 0.65 BSC 0.38 0.22 8° 4° 0° SEATING PLANE 0.95 0.75 0.55 060106-A 0.05 MIN COPLANARITY 0.10 0.25 0.09 1.85 1.75 1.65 2.00 MAX COMPLIANT TO JEDEC STANDARDS MO-150-AH Figure 28. 28-Lead Shrink Small Outline Package [SSOP] (RS-28) Dimensions shown in millimeters 0.30 0.25 0.18 32 25 1 24 0.50 BSC 0.80 0.75 0.70 SEATING PLANE 0.50 0.40 0.30 3.65 3.50 SQ 3.
PAGE 22
AD5544/AD5554 Data Sheet ORDERING GUIDE Model 1 AD5544ARS AD5544ARSZ AD5544ARSZ-REEL7 AD5544BRSZ AD5544BRSZ-REEL7 AD5544ACPZ-1-R2 AD5544ACPZ-1-RL7 AD5544BCPZ-R2 AD5544BCPZ-RL7 AD5554BRSZ EV-AD5544/45SDZ 1 RES Bit 16 16 16 16 16 16 16 16 16 14 INL LSB ±2 ±2 ±2 ±1 ±1 ±4 ±4 ±1 ±1 ±0.5 DNL LSB ±1.5 ±1.5 ±1.
PAGE 23
Data Sheet AD5544/AD5554 NOTES Rev.
PAGE 24
AD5544/AD5554 Data Sheet NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2000–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00943-0-5/13(G) Rev.