Datasheet

AD5543/AD5553 Data Sheet
Rev. F | Page 6 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
CLK
1
SDI
2
R
FB
3
V
REF
4
CS
8
V
DD
7
GND
6
I
OUT
5
AD5543/
AD5553
TOP VIEW
(Not to Scale)
02917-004
Figure 6. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1 CLK Clock Input. Positive-edge triggered, clocks data into shift register.
2 SDI Serial Register Input. Data loads directly into the shift register MSB first. Extra leading bits are ignored.
3 R
FB
Internal Matching Feedback Resistor. This pin connects to an external op amp for voltage output.
4 V
REF
DAC Reference Input Pin. Establishes DAC full-scale voltage. Constant input resistance vs. code.
5 I
OUT
DAC Current Output. This pin connects to the inverting terminal of the external precision I-to-V op amp for
voltage output.
6 GND Analog and Digital Ground.
7 V
DD
Positive Power Supply Input. Specified range of operation at 5 V ± 10%.
8
CS Chip Select. Active low digital input. Transfers shift-register data to DAC register on rising edge.
See Table 4 for operation.
Table 4. Control-Logic Truth Table
CLK
CS
Serial Shift Register Function DAC Register
X H No effect Latched
↑
+
1
L
Shift register data advanced one bit
Latched
X
1
H No effect Latched
X
1
↑
+
1
Shift register data transferred to DAC register New data loaded from serial register
1
↑+ = positive logic transition; X = don't care.