Datasheet

AD5543/AD5553 Data Sheet
Rev. F | Page 4 of 20
Parameter Symbol Condition 5 V ± 10% Unit
AC CHARACTERISTICS
4
Output Voltage Settling Time t
S
To ±0.1% of full scale, 0.5 µs typ
Data = 0x0000 to 0xFFFF to 0x0000 for AD5543
Data = 0x0000 to 0x3FFF to 0x0000 for AD5553
Reference Multiplying Bandwidth
BW
V
REF
= 100 mV rms, data = 0xFFFF
6.6
MHz typ
DAC Glitch Impulse Q V
REF
= 0 V, data = 0x7FFF to 0x8000 for AD5543 7 nV-sec
Feedthrough Error V
OUT
/V
REF
Data = 0x0000, V
REF
= 100 mV rms, same channel −83 dB
Digital Feedthrough Q C
S
= 1 and f
CLK
= 1 MHz 7 nV-sec
Total Harmonic Distortion THD V
REF
= 5 V p-p, data = 0xFFFF, f = 1 kHz −103 dB typ
Output Spot Noise Voltage e
N
f = 1 kHz, BW = 1 Hz 12 nV/√Hz
1
All static performance tests (except I
OUT
) are performed in a closed-loop system using an external precision OP177 I-to-V converter amplifier. The AD5543 R
FB
terminal is
tied to the amplifier output. The +IN op amp is grounded, and the DAC I
OUT
is tied to the −IN op amp. Typical values represent average readings measured at 25°C.
2
These parameters are guaranteed by design and are not subject to production testing.
3
All ac characteristic tests are performed in a closed-loop system using an AD8038 I-to-V converter amplifier except for THD where an AD8065 was used.
4
All input control signals are specified with t
R
= t
F
= 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
TIMING DIAGRAMS
SDI
CLK
CS
t
CSH
t
CSS
t
DS
t
DH
t
CH
t
CL
D15 D14 D13 D12 D11 D10
D9 D8 D1 D0
02917-016
Figure 4. AD5543 Timing Diagram
t
CSH
t
CSS
t
DS
t
DH
t
CH
t
CL
SDI
CLK
CS
D13 D12 D11 D10 D9 D8 D7 D6 D1 D0
02917-017
Figure 5. AD5553 Timing Diagram