Datasheet

AD5551/AD5552
Rev. A | Page 6 of 16
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
V
OUT
1
AGND 2
V
REF
3
CS
4
V
DD
8
DGND 7
DIN 6
SCLK
5
AD5551
TOP VIEW
(Not to Scale)
01943-004
Figure 4. AD5551 Pin Configuration
RFB 1
V
OUT
2
AGNDF 3
AGNDS 4
V
DD
14
INV 13
DGND 12
LDAC 11
V
REFS
5
DIN
10
V
REFF
6
NC
9
CS
7
SCLK
8
AD5552
TOP VIEW
(Not to Scale)
NC = NO CONNECNT
01943-005
Figure 5. AD5552 Pin Configuration
Table 4. AD5551 Pin Function Descriptions
Pin No. Mnemonic Description
1 V
OUT
Analog Output Voltage from the DAC.
2 AGND Ground Reference Point for Analog Circuitry.
3 V
REF
This is the voltage reference input for the DAC. Connect to external reference ranges from 2 V to V
DD
.
4
CS
This is an active low-logic input signal. The chip select signal is used to frame the serial data input.
5 SCLK
Clock Input. Data is clocked into the input register on the rising edge of SCLK. Duty cycle must be between 40%
and 60%.
6 DIN
Serial Data Input. This device accepts 14-bit words. Data is clocked into the input register on the rising edge of SCLK.
7 DGND
Digital Ground. Ground reference for digital circuitry.
8 V
DD
Analog Supply Voltage, 2.7 V to 5.5 V ± 10%.
Table 5. AD5552 Pin Function Descriptions
Pin No. Mnemonic Description
1 RFB Feedback Resistor. In bipolar mode, connect this pin to external op amp output.
2 V
OUT
Analog Output Voltage from the DAC.
3 AGNDF
Ground Reference Point for Analog Circuitry (Force).
4 AGNDS
Ground Reference Point for Analog Circuitry (Sense).
5 V
REFS
This is the voltage reference input (sense) for the DAC. Connect to external reference ranges from 2 V to V
DD
.
6 V
REFF
This is the voltage reference input (force) for the DAC. Connect to external reference ranges from 2 V to V
DD
.
7
CS
This is an active low-logic input signal. The chip select signal is used to frame the serial data input.
8 SCLK
Clock input. Data is clocked into the input register on the rising edge of SCLK. Duty cycle must be between 40%
and 60%.
9 NC
No Connect.
10 DIN
Serial Data Input. This device accepts 14-bit words. Data is clocked into the input register on the rising edge of SCLK.
11
LDAC
LDAC Input. When this input is taken low, the DAC register is simultaneously updated with the contents of the
input register.
12 DGND Digital Ground. Ground reference for digital circuitry.
13 INV
Connected to the internal scaling resistors of the DAC. Connect the INV pin to external op amps inverting input in
bipolar mode.
14 V
DD
Analog Supply Voltage, 2.7 V to 5.5 V ± 10%.