Datasheet

AD5551/AD5552
Rev. A | Page 4 of 16
TIMING CHARACTERISTICS
V
DD
= 2.7 V to 5.5 V, 2.5 V ≤ V
REF
≤ 5.5 V, AGND = DGND = 0 V. All specifications −40°C ≤ T
A
≤ +85°C, unless otherwise noted.
Table 2.
Limit at T
MIN
, T
MAX
Parameter
1, 2
All Versions Unit Description
f
SCLK
25 MHz max SCLK cycle frequency
t
1
40 ns min SCLK cycle time
t
2
20 ns min SCLK high time
t
3
20 ns min SCLK low time
t
4
15 ns min
CS
low to SCLK high setup
t
5
15 ns min
CS
high to SCLK high setup
t
6
35 ns min
SCLK high to CS
low hold time
t
7
20 ns min
SCLK high to CS
high hold time
t
8
15 ns min Data setup time
t
9
0 ns min Data hold time
t
10
30 ns min
LDAC
pulse width
t
11
30 ns min
CS
high to LDAC low setup
t
12
30 ns min
CS
high time between active periods
1
Guaranteed by design, not production tested.
2
Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are measured with tr = tf = 5 ns (10% to
90% of +3 V and timed from a voltage level of +1.6 V).
SCLK
CS
DIN
LDAC*
DB13 DB0
t
6
t
4
t
12
t
8
t
9
t
2
t
3
t
1
t
7
t
5
t
10
t
11
*AD5552 ONLY. MAY BE TIED PERMANENTLY LOW IF REQUIRED.
01943-003
Figure 3. Timing Diagram