Datasheet

AD5551/AD5552
Rev. A | Page 12 of 16
Assuming a perfect reference, the worst-case output voltage
may be calculated from the following equation:
()
INLVVV
D
V
ZSE
GE
REF
UNIOUT
+++×=
−
14
2
where:
V
OUT–UNI
is the unipolar mode worst-case output.
D is the decimal code loaded to the DAC.
V
REF
is the reference voltage applied to part.
V
GE
is the gain error in volts.
V
ZSE
is the zero-scale error in volts.
INL is the integral nonlinearity in volts.
BIPOLAR OUTPUT OPERATION
With the aid of an external op amp, the AD5552 may be confi-
gured to provide a bipolar voltage output. A typical circuit of
such operation is shown in Figure 24. The matched bipolar
offset resistors R
FB
and R
INV
are connected to an external op amp
to achieve this bipolar output swing where R
FB
= R
INV
= 28 k.
Table 7 shows the transfer function for this output operating
mode. Also provided on the AD5552 are a set of Kelvin
connections to the analog ground inputs.
+5V
–5V
V
OUT
INV
RFB
V
REFF
AGNDF AGNDS
V
DD
DIN
SCLK
CS
AD5552
V
REFS
DGND
+
0.1µF0.1µF
10µF
UNIPOLAR
OUTPUT
EXTERNAL
OP AMP
2.5
V
5
V
LDAC
SERIAL
INTERFACE
R
INV
R
FB
01943-024
Figure 24. Bipolar Output (AD5552 Only)
Table 7. Bipolar Code Table
DAC Latch Contents
MSB LSB Analog Output
11 1111 1111 1111 +V
REF
× (8191/8192)
10 0000 0000 0000 +V
REF
× (1/8192)
00 0000 0000 0001 0 V
00 0000 0000 0000 −V
REF
× (1/8192)
00 0000 0000 0000 −V
REF
× (8191/8192) = –V
REF
Assuming a perfect reference, the worst-case bipolar output
voltage may be calculated from the following equation.
ARD
RDVRDVV
V
REF
OS
UNIOUT
BIPOUT
/)2(1
)1()2)([(
++
+
−+
+
=
−
−
where:
V
OS
is the external op amp input offset voltage.
RD is the R
FB
and R
IN
resistor matching error, unitless.
A is the op amp open-loop gain.
OUTPUT AMPLIFIER SELECTION
For bipolar mode, use a precision amplifier, supplied from a
dual power supply. This provides the ±V
REF
output. In a single-
supply application, selection of a suitable op amp may be more
difficult as the output swing of the amplifier does not usually
include the negative rail, in this case AGND. This can result in
some degradation of the specified performance unless the
application does not use codes near zero.
The selected op amp needs to have a very low-offset voltage,
(the DAC LSB is 152 µV with a 2.5 V reference), to eliminate
the need for output offset trims. Input bias current should also
be very low as the bias current multiplied by the DAC output
impedance (approximately 6K) adds to the zero-code error.
Rail-to-rail input and output performance is required. For fast
settling, the slew rate of the op amp should not impede the
settling time of the DAC. Output impedance of the DAC is
constant and code-independent, but to minimize gain errors,
the input impedance of the output amplifier should be as high
as possible. The amplifier should also have a 3 dB bandwidth of
1 MHz or greater. The amplifier adds another time constant to
the system, therefore increasing the settling time of the output.
A higher 3 dB amplifier bandwidth results in a faster effective
settling time of the combined DAC and amplifier.
FORCE SENSE BUFFER AMPLIFIER SELECTION
These amplifiers can be single-supply or dual supplies, low
noise amplifiers. A low-output impedance at high frequencies
is preferred as they need to be able to handle dynamic currents
of up to ±20 mA.