Datasheet
Data Sheet AD5546/AD5556
Rev. D | Page 11 of 20
DIGITAL SECTION
The AD5546/AD5556 have 16-/14-bit parallel inputs. The devices are double buffered with 16-/14-bit registers. The double-buffered
feature allows the update of several AD5546/AD5556 simultaneously. For the AD5546, the input register is loaded directly from a 16-bit
controller bus when the
WR
pin is brought low. The DAC register is updated with data from the input register when LDAC is brought
high. Updating the DAC register updates the DAC output with the new data (see Figure 17). To make both registers transparent, tie
WR
low and LDAC high. The asynchronous
RS
pin resets the part to zero scale if the MSB pin = 0 and to midscale if the MSB pin = 1.
Table 5. AD5546 Parallel Input Data Format
MSB LSB
Bit Position B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
Data Word D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Table 6. AD5556 Parallel Input Data Format
MSB LSB
Bit Position B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
Data Word D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Table 7. Control Inputs
RS
WR
LDAC Register Operation
0 X
1
X
1
Reset output to 0, with MSB pin = 0 and to midscale with MSB pin = 1.
1 0 0 Load input register with data bits.
1 1 1 Load DAC register with the contents of the input register.
1 0 1 Input and DAC registers are transparent.
1
When LDAC and
WR
are tied together and programmed as a pulse, the data bits are loaded into the input register on
the falling edge of the pulse and then loaded into the DAC register on the rising edge of the pulse.
1 1 0 No register operation.
1
X = don’t care.
ESD PROTECTION CIRCUITS
All logic input pins contain back-biased ESD protection Zeners
connected to ground (GND) and V
DD
, as shown in Figure 18. As
a result, the voltage level of the logic input should not be greater
than the supply voltage.
03810-020
5kΩ
DIGITAL
INPUTS
DGND
V
DD
Figure 18. Equivalent ESD Protection Circuits
AMPLIFIER SELECTION
In addition to offset voltage, the bias current is important in op
amp selection for precision current output DACs. An input bias
current of 30 nA in the op amp contributes to 1 LSB in the
AD5546’s full-scale error. The OP1177 and AD8628 op amps
are good candidates for the I-V conversion.
REFERENCE SELECTION
The initial accuracy and the rated output of the voltage refer-
ence determine the full span adjustment. The initial accuracy is
usually a secondary concern in precision because it can be
trimmed. Figure 23 shows an example of a trimming circuit.
The zero scale error can also be minimized by standard op amp
nulling techniques.
The voltage reference temperature coefficient (TC) and long-
term drift are primary considerations. For example, a 5 V ref-
erence with a TC of 5 ppm/
o
C means that the output changes by
25 µV per degree Celsius. As a result, the reference that operates
at 55
o
C contributes an additional 750 µV full-scale error.
Similarly, the same 5 V reference with a ±50 ppm long-term
drift means that the output may change by ±250 µV over time.
Therefore, it is practical to calibrate a system periodically to
maintain its optimum precision.