Datasheet

Data Sheet AD5545/AD5555
Rev. G | Page 11 of 24
Table 7. AD5545 Control Logic Truth Table
1, 2
CS
CLK
LDAC RS
MSB Serial Shift Register Function Input Register Function DAC Register
H X H H X No effect Latched Latched
L L H H X No effect Latched Latched
L
+
H H X Shift register data advanced one bit Latched Latched
L H H H X No effect Latched Latched
+
L H H X No effect
Selected DAC updated
with current SR current
Latched
H X L H X No effect Latched Transparent
H X H H X No effect Latched Latched
H X
+
H X No effect Latched Latched
H X H L 0 No effect Latched data = 0x0000 Latched data = 0x0000
H X H L H No effect Latched data = 0x8000 Latched data = 0x8000
1
SR = shift register, + = positive logic transition, and X = don’t care.
2
At power-on, both the input register and the DAC register are loaded with all 0s.
Table 8. AD5555 Control Logic Truth Table
1, 2
CS
CLK
LDAC RS
MSB Serial Shift Register Function Input Register Function DAC Register
H X H H X No effect Latched Latched
L L H H X No effect Latched Latched
L
+
H H X Shift register data advanced one bit Latched Latched
L H H H X No effect Latched Latched
+
L H H X No effect
Selected DAC updated
with current SR current
Latched
H X L H X No effect Latched Transparent
H X H H X No effect Latched Latched
H X
+
H X No effect Latched Latched
H X H L 0 No effect Latched data = 0x0000 Latched data = 0x0000
H X H L H No effect Latched data = 0x2000 Latched data = 0x2000
1
SR = shift register, + = positive logic transition, and X = don’t care.
2
At power-on, both the input register and the DAC register are loaded with all 0s.
POWER-UP SEQUENCE
It is recommended to power-up V
DD
and ground prior to any
reference voltages. The ideal power-up sequence is A
GND
x,
DGND, V
DD
, V
REF
x, and digital inputs. A noncompliance
power-up sequence can elevate reference current, but the device
will resume normal operation once V
DD
is powered.
LAYOUT AND POWER SUPPLY BYPASSING
It is a good practice to employ compact, minimum lead length
layout design. The input leads should be as direct as possible
with a minimum conductor length. Ground paths should have
low resistance and low inductance.
Similarly, it is also good practice to bypass the power supplies
with quality capacitors for optimum stability. Supply leads to
the device should be bypassed with 0.01 μF to 0.1 μF disc or
chip ceramic capacitors. Low ESR 1 μF to 10 μF tantalum or
electrolytic capacitors should also be applied at V
DD
to minimize
any transient disturbance and to filter any low frequency ripple
(see Figure 20). Users should not apply switching regulators for
V
DD
due to the power supply rejection ratio degradation over
frequency.
AD5545/
AD5555
V
DD
V
DD
A
GND
X
DGND
02918-0-008
C1
+
C2
10F 0.1F
Figure 20. Power Supply Bypassing and Grounding Connection
GROUNDING
The DGND and A
GND
x pins of the AD5545/AD5555 refer to the
digital and analog ground references. To minimize the digital
ground bounce, the DGND terminal should be joined remotely
at a single point to the analog ground plane (see Figure 20).