Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - DA converter (DAC) SOIC 8

2.7 V to 5.5 V, Serial-Input,

Voltage-Output, 16-Bit DACs

Data Sheet

AD5541/AD5542

Rev. F

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FEATURES

Full 16-bit performance

3 V and 5 V single-supply operation

Low 0.625 mW power dissipation

1 µs settling time

Unbuffered voltage output capable of driving 60 kΩ

loads directly

SPI-/QSPI-/MICROWIRE-compatible interface standards

Power-on reset clears DAC output to 0 V (unipolar mode)

5 kV HBM ESD classification

Low glitch: 1.1 nV-sec

APPLICATIONS

Digital gain and offset adjustment

Automatic test equipment

Data acquisition systems

Industrial process control

GENERAL DESCRIPTION

The AD5541/AD5542 are single, 16-bit, serial input, voltage

output digital-to-analog converters (DACs) that operate from

a single 2.7 V to 5.5 V supply. The DAC output range extends

from 0 V to V

REF

The DAC output range extends from 0 V to V

REF

and is guaranteed

monotonic, providing 1 LSB INL accuracy at 16 bits without

adjustment over the full specified temperature range of −40°C to

+85°C. Offering unbuffered outputs, the AD5541/AD5542

achieve a 1 µs settling time with low power consumption and low

offset errors. Providing a low noise performance of 11.8 nV/√Hz

and low glitch, the AD5541/AD5542 is suitable for deployment

across multiple end systems.

The AD5542 can be operated in bipolar mode, which generates

a ±V

REF

output swing. The AD5542 also includes Kelvin sense

connections for the reference and analog ground pins to reduce

layout sensitivity.

The AD5541/AD5542 utilize a versatile 3-wire interface that is

compatible with SPI, QSPI™, MICROWIRE™ and DSP interface

standards. The AD5541/AD5542 are available in 8-lead and

14-lead SOIC packages.

FUNCTIONAL BLOCK DIAGRAMS

16-BIT DAC

16-BIT DAC LATCH

SERIAL INPUT REGISITER

DGND

DIN

REF

SCLK

OUT

AGND

AD5541

CONTROL

LOGIC

07557-001

Figure 1. AD5541

16-BIT DAC

16-BIT DAC LATCH

SERIAL INPUT REGISITER

DGND

LDAC

REFF

DIN

REFS

OUT

INV

RFB

AGNDF

AGNDS

AD5542

CONTROL

LOGIC

07557-002

SCLK

INV

Figure 2. AD5542

Table 1.

Part No.

Description

AD5541A/AD5542A

Single, 16-bit unbuffered nanoDAC™,

±1 LSB INL, LFCSP

AD5024/AD5044/AD5064

Quad 12-/14-/16-bit nanoDAC,

±1 LSB INL, TSSOP

AD5062

Single, 16-bit nanoDAC, ±1 LSB INL,

SOT-23

AD5063

Single, 16-bit nanoDAC, ±1 LSB INL,

SOT-23

PRODUCT HIGHLIGHTS

1. Single-Supply Operation. The AD5541 and AD5542 are fully

specified and guaranteed for a single 2.7 V to 5.5 V supply.

2. Low Power Consumption. These parts consume typically

0.625 mW with a 5 V supply and 0.375 mV at 3 V.

3. 3-Wire Serial Interface.

4. Unbuffered Output Capable of Driving 60 kΩ Loads. This

reduces power consumption because there is no internal

buffer to drive.

5. Power-On Reset Circuitry.

Summary of content (20 pages)

PAGE 1
2.7 V to 5.5 V, Serial-Input, Voltage-Output, 16-Bit DACs AD5541/AD5542 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAMS VDD Full 16-bit performance 3 V and 5 V single-supply operation Low 0.625 mW power dissipation 1 µs settling time Unbuffered voltage output capable of driving 60 kΩ loads directly SPI-/QSPI-/MICROWIRE-compatible interface standards Power-on reset clears DAC output to 0 V (unipolar mode) 5 kV HBM ESD classification Low glitch: 1.
PAGE 2
AD5541/AD5542 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Bipolar Output Operation ......................................................... 12 Applications ....................................................................................... 1 Output Amplifier Selection ....................................................... 12 General Description ..............................................................
PAGE 3
Data Sheet AD5541/AD5542 SPECIFICATIONS VDD = 2.7 V to 5.5 V, 2.5 V ≤ VREF ≤ VDD, AGND = DGND = 0 V. All specifications TA = TMIN to TMAX, unless otherwise noted. Table 2. Parameter 1 STATIC PERFORMANCE Resolution Relative Accuracy (INL) Min Typ Max Differential Nonlinearity (DNL) ±0.5 ±0.5 ±0.5 ±0.5 Gain Error +0.5 ±1.0 ±2.0 ±4.0 ±1.0 ±1.5 ±2 ±3 Gain Error Temperature Coefficient Unipolar Zero Code Error ±0.1 ±0.3 Unipolar Zero Code Temperature Coefficient AD5542 Bipolar Resistor Matching ±0.
PAGE 4
AD5541/AD5542 Data Sheet Parameter 1 POWER REQUIREMENTS VDD IDD Power Dissipation 1 2 3 Min Typ Max Unit 125 0.625 5.5 150 0.825 V μA mW 2.7 Test Conditions Digital inputs at rails Temperature ranges are as follows: A, B, C versions: −40°C to +85°C; J, L versions: 0°C to 70°C. Reference input resistance is code-dependent, minimum at 0x8555. Guaranteed by design, not subject to production test. TIMING CHARACTERISTICS VDD = 2.7 V to 5.5 V ±10%, VREF = 2.
PAGE 5
Data Sheet AD5541/AD5542 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 4.
PAGE 6
AD5541/AD5542 Data Sheet VOUT 1 AGND 2 AD5541 REF 3 TOP VIEW CS 4 (Not to Scale) 8 VDD 7 DGND 6 DIN 5 SCLK 07557-004 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 4. AD5541 Pin Configuration Table 5. AD5541 Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 Mnemonic VOUT AGND REF CS SCLK DIN DGND VDD Description Analog Output Voltage from the DAC. Ground Reference Point for Analog Circuitry. Voltage Reference Input for the DAC. Connect to an external 2.5 V reference.
PAGE 7
Data Sheet AD5541/AD5542 TYPICAL PERFORMANCE CHARACTERISTICS 0.50 0.50 0 –0.25 –0.50 –0.75 0 8192 16384 24576 32768 40960 49152 CODE 57344 65536 VDD = 5V VREF = 2.5V 0.25 0 –0.25 –0.50 0 8192 Figure 6. Integral Nonlinearity vs. Code 0.75 0 –0.25 –0.50 –0.75 –40 –20 0 20 40 60 80 TEMPERATURE (°C) 100 120 140 0.50 0.25 0 –0.25 –0.50 –60 07557-007 –1.00 –60 VDD = 5V VREF = 2.5V Figure 7. Integral Nonlinearity vs.
PAGE 8
AD5541/AD5542 Data Sheet 0 0.15 VDD = 5V VREF = 2.5V TA = 25°C –0.1 0.10 ZERO-CODE ERROR (LSB) GAIN ERROR (LSB) –0.2 –0.3 –0.4 –0.5 –0.6 –0.7 VDD = 5V VREF = 2.5V TA = 25°C 0.05 0 –0.05 –0.10 –40 25 TEMPERATURE (°C) 85 –0.15 08898-012 –0.9 Figure 12. Gain Error vs. Temperature 25 TEMPERATURE (°C) 85 Figure 15. Zero-Code Error vs. Temperature 2.0 132 TA = 25°C VDD = 5V VREF = 2.5V 130 TA = 25°C 128 SUPPLY CURRENT (µA) SUPPLY CURRENT (µA) –40 08898-015 –0.8 126 124 122 120 1.
PAGE 9
Data Sheet AD5541/AD5542 VREF = 2.5V VDD = 5V TA = 25°C VREF = 2.5V VDD = 5V TA = 25°C 2µs/DIV 100 100 DIN (5V/DIV) CS (5V/DIV) 10pF 50pF 100pF 200pF VOUT (50mV/DIV) 10 VOUT (0.5V/DIV) 08898-018 2µs/DIV Figure 18. Digital Feedthrough 08898-020 10 Figure 20. Large Signal Settling Time 1.236 5 CS 0 1.234 VREF = 2.5V VDD = 5V TA = 25°C –5 100 • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • VOUT (1V/DIV) 90 –10 1.230 –15 1.
PAGE 10
AD5541/AD5542 Data Sheet TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) For the DAC, relative accuracy or INL is a measure of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. A typical INL vs. code plot can be seen in Figure 6. Differential Nonlinearity (DNL) DNL is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes.
PAGE 11
Data Sheet AD5541/AD5542 THEORY OF OPERATION The AD5541/AD5542 are single, 16-bit, serial input, voltage output DACs. They operate from a single supply ranging from 2.7 V to 5.5 V and consume typically 125 µA with a supply of 5 V. Data is written to these devices in a 16-bit word format, via a 3- or 4-wire serial interface. To ensure a known power-up state, these parts are designed with a power-on reset function.
PAGE 12
AD5541/AD5542 Data Sheet Assuming a perfect reference, the unipolar worst-case output voltage can be calculated from the following equation: VOUT-UNI = Assuming a perfect reference, the worst-case bipolar output voltage can be calculated from the following equation: D × (VREF + VGE ) + V ZSE + INL 216 VOUT-BIP = [(V OUT − UNI ] ) + VOS (2 + RD ) − VREF (1 + RD ) 1 + (2 + RD ) A where: VOUT−UNI is unipolar mode worst-case output. D is code loaded to DAC.
PAGE 13
Data Sheet AD5541/AD5542 POWER-ON RESET POWER SUPPLY AND REFERENCE BYPASSING The AD5541/AD5542 have a power-on reset function to ensure that the output is at a known state on power-up. On power-up, the DAC register contains all 0s until the data is loaded from the serial register. However, the serial register is not cleared on power-up, so its contents are undefined. When loading data initially to the DAC, 16 bits or more should be loaded to prevent erroneous data appearing on the output.
PAGE 14
AD5541/AD5542 Data Sheet MICROPROCESSOR INTERFACING AD5541/AD5542 TO MICROWIRE INTERFACE Figure 27 shows an interface between the AD5541/AD5542 and any MICROWIRE-compatible device. Serial data is shifted out on the falling edge of the serial clock and into the AD5541/ AD5542 on the rising edge of the serial clock. No glue logic is required because the DAC clocks data into the input shift register on the rising edge.
PAGE 15
Data Sheet AD5541/AD5542 APPLICATIONS INFORMATION OPTOCOUPLER INTERFACE DECODING MULTIPLE AD5541/AD5542s The digital inputs of the AD5541/AD5542 are Schmitt-triggered so that they can accept slow transitions on the digital input lines. This makes these parts ideal for industrial applications where it may be necessary to isolate the DAC from the controller via optocouplers. Figure 29 illustrates such an interface. The CS pin of the AD5541/AD5542 can be used to select one of a number of DACs.
PAGE 16
AD5541/AD5542 Data Sheet OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890) 5 1 6.20 (0.2441) 5.80 (0.2284) 4 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) 1.75 (0.0688) 1.35 (0.0532) 0.51 (0.0201) 0.31 (0.0122) COPLANARITY 0.10 SEATING PLANE 0.50 (0.0196) 0.25 (0.0099) 45° 8° 0° 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.
PAGE 17
Data Sheet AD5541/AD5542 ORDERING GUIDE Model 1 AD5541CR AD5541CRZ AD5541CRZ-REEL7 AD5541LR AD5541LR-REEL7 AD5541LRZ AD5541LRZ-REEL7 AD5541BR AD5541BRZ AD5541BRZ-REEL AD5541JR AD5541JR-REEL7 AD5541JRZ AD5541JRZ-REEL7 AD5541AR AD5541AR-REEL7 AD5541ARZ AD5541ARZ-REEL7 AD5542CR AD5542CR-REEL7 AD5542CRZ AD5542CRZ-REEL7 AD5542LR AD5542LRZ AD5542BR AD5542BRZ AD5542BRZ-REEL7 AD5542JR AD5542JR-REEL7 AD5542JRZ AD5542JRZ-REEL7 AD5542AR AD5542AR-REEL7 AD5542ARZ AD5542ARZ-REEL7 EVAL-AD5541/42EBZ 1 INL ±1 LSB ±1 LSB
PAGE 18
AD5541/AD5542 Data Sheet NOTES Rev.
PAGE 19
Data Sheet AD5541/AD5542 NOTES Rev.