Datasheet

AD5541A
Rev. A | Page 5 of 20
TIMING CHARACTERISTICS
V
DD
= 5 V, 2.5 V ≤ V
REF
≤ V
DD
, V
INH
= 90% of V
LOGIC
, V
INL
= 10% of V
LOGIC
, AGND = DGND = 0 V, −40°C < T
A
< +105°C, unless otherwise
noted.
Table 4.
Parameter
1, 2
Limit at
1.8 ≤ V
LOGIC
≤ 2.7 V
Limit at
2.7 V ≤ V
LOGIC
≤ 5.5 V
Unit Description
f
SCLK
14 50 MHz max SCLK cycle frequency
t
1
70 20 ns min SCLK cycle time
t
2
35 10 ns min SCLK high time
t
3
35 10 ns min SCLK low time
t
4
5 5 ns min
CS
low to SCLK high setup
t
5
5 5 ns min
CS
high to SCLK high setup
t
6
5 5 ns min
SCLK high to CS
low hold time
t
7
10 5 ns min
SCLK high to CS
high hold time
t
8
35 10 ns min Data setup time
t
9
5 4 ns min Data hold time (V
INH
= 90% of V
DD
, V
INL
= 10% of V
DD
)
t
9
5 5 ns min Data hold time (V
INH
= 3 V, V
INL
= 0 V)
t
10
20 20 ns min
LDAC
pulse width
t
11
10 10 ns min
CS
high to LDAC low setup
t
12
15 15 ns min
CS
high time between active periods
1
Guaranteed by design and characterization. Not production tested.
2
All input signals are specified with t
R
= t
F
= 1 ns/V and timed from a voltage level of (V
INL
+ V
INH
)/2.
SCLK
CS
DIN
DB15
LDAC
t
6
t
4
t
12
t
8
t
9
t
2
t
3
t
1
t
7
t
5
t
11
t
10
08516-003
Figure 3. Timing Diagram