Datasheet

AD5541A
Rev. A | Page 14 of 20
THEORY OF OPERATION
The AD5541A is a single, 16-bit, serial input, voltage output
DAC. It operates from a single supply ranging from 2.7 V to 5 V
and consumes typically 125 µA with a supply of 5 V. Data is written
to these devices in a 16-bit word format, via a 3- or 4-wire serial
interface. To ensure a known power-up state, this part is designed
with a power-on reset function. The output is reset to 0 V.
DIGITAL-TO-ANALOG SECTION
The DAC architecture consists of two matched DAC sections.
A simplified circuit diagram is shown in Figure 30. The DAC
architecture of the AD5541A is segmented. The four MSBs of
the 16-bit data-word are decoded to drive 15 switches, E1 to
E15. Each switch connects one of 15 matched resistors to either
AGND or V
REF
. The remaining 12 bits of the data-word drive
the S0 to S11 switches of a 12-bit voltage mode R-2R ladder
network.
2R . . . . .
S1 . . . . .
2R
S11
2R
E1
2R . . . . .
E2 . . . . .
2R 2R
S0
2R
E15
R R
V
REF
V
OUT
12-BIT R-2R LADDER
FOUR MSBs DECODED
INTO 15 EQUAL SEGMENTS
08516-022
Figure 30. DAC Architecture
With this type of DAC configuration, the output impedance is
independent of code, whereas the input impedance seen by the
reference is heavily code dependent. The output voltage is
dependent on the reference voltage, as shown in the following
equation:
N
REF
OUT
DV
V
2
×
=
where:
D is the decimal data-word loaded to the DAC register.
N is the resolution of the DAC.
For a reference of 2.5 V, the equation simplifies to the following:
536,65
5.2 D
V
OUT
×
=
This gives a V
OUT
of 1.25 V with midscale loaded and 2.5 V with
full scale loaded to the DAC.
The LSB size is V
REF
/65,536.
SERIAL INTERFACE
The AD5541A is controlled by a versatile 3- or 4-wire serial
interface that operates at clock rates of up to 50 MHz and is
compatible with SPI, QSPI, MICROWIRE, and DSP interface
standards. The timing diagram is shown in Figure 3. The
AD5541A has a separate serial input register from the 16-bit
DAC register that allows preloading of a new data value into the
serial input register without disturbing the present DAC output
voltage.
Input data is framed by the chip select input,
CS
. After a high-
to-low transition on
CS
, data is shifted synchronously and
latched into the serial input register on the rising edge of the
serial clock, SCLK. After 16 data bits have been loaded into the
serial input register, a low-to-high transition on
CS
transfers the
contents of the shift register to the DAC register if
LDAC
is held
low. If
LDAC
is high at this point, a low-to-high transition on
CS
transfers the contents into the serial input register only.
After a new value is fully loaded in the serial input register, it
can be asynchronously transferred to the DAC register by
strobing the
LDAC
pin. Data is loaded MSB first in 16-bit
words. Data can be loaded to the part only while
CS
is low.