Datasheet

AD5532
Rev. D | Page 7 of 20
SERIAL INTERFACE
Table 4.
Parameter
1, 2
Limit at T
MIN
, T
MAX
(A Version) Unit Conditions/Comments
f
CLKIN
3
14 MHz max SCLK frequency
t
1
28 ns min SCLK high pulse width
t
2
28 ns min SCLK low pulse width
SYNC
falling edge to SCLK falling edge setup time
t
3
15 ns min
SYNC
low time
t
4
50 ns min
t
5
10 ns min D
IN
setup time
t
6
5 ns min D
IN
hold time
SYNC
falling edge to SCLK rising edge setup time for read back
t
7
5 ns min
t
8
4
20 ns max SCLK rising edge to D
OUT
valid
t
9
4
60 ns max
SCLK falling edge to D
OUT
high impedance
10th SCLK falling edge to
SYNC
falling edge for read back
t
10
400 ns min
24th SCLK falling edge to
SYNC
falling edge for DAC mode write
t
11
400 ns min
SCLK falling edge to
SYNC
falling edge setup time for read back
t
12
5
7 ns min
00939-C-004
t
1
t
3
t
2
MSB LSB
SCLK
12345678910
SYNC
D
IN
t
4
t
5
t
6
Figure 4. 10-Bit Write (ISHA Mode and Both Readback Modes)
00939-C-005
SCLK
12345 21222324 1
D
IN
SYNC
t
1
t
3
t
2
t
4
t
5
t
6
LSBMSB
t
11
Figure 5. 24-Bit Write (DAC Mode)
00939-C-006
SCLK
10 1234567891011121314
MSB LSB
D
OUT
SYNC
t
7
t
1
t
2
t
12
t
4
t
8
t
10
t
9
Figure 6. 14-Bit Read (Both Readback Modes)
1
See Figure 4, Figure 5, and Figure 6.
2
Guaranteed by design and characterization, not production tested.
3
In ISHA mode the maximum SCLK frequency is 20 MHz and the minimum pulse width is 20 ns.
4
These numbers are measured with the load circuit of Figure 3.
5
SYNC
should be taken low while SCLK is low for read back.