Datasheet

AD5532
Rev. D | Page 6 of 20
TIMING CHARACTERISTICS
PARALLEL INTERFACE
Table 3.
Parameter
1, 2
Limit at T
MIN
, T
MAX
(A Version) Unit Conditions/Comments
t
1
0 ns min
CS
to WR setup time
t
2
0 ns min
CS
to WR hold time
t
3
50 ns min
CS
pulse width low
t
4
50 ns min
WR
pulse width low
t
5
20 ns min
A4–A0, CAL, OFFS_SEL to WR
setup time
t
6
7 ns min
A4–A0, CAL, OFFS_SEL to WR
hold time
1
See Figure 2 and Figure 3, the parallel interface timing diagrams.
2
PARALLEL INTERFACE TIMING DIAGRAMS
Guaranteed by design and characterization, not production tested.
00939-C-002
A4–A0, CAL,
OFFS_SEL
t
1
t
3
t
2
t
4
t
5
t
6
CS
WR
Figure 2. Parallel Write (ISHA Mode Only)
00939-C-003
200μAI
OL
200μAI
OH
1.6V
TO OUTPUT
PIN
C
L
50pF
Figure 3. Load Circuit for D
OUT
Timing Specifications