Datasheet

AD5532
Rev. D | Page 16 of 20
SERIAL INTERFACE
The serial interface allows easy interfacing to most micro-
controllers and DSPs, such as the PIC16C, PIC17C, QSPI, SPI,
DSP56000, TMS320, and ADSP-21xx, without the need for any
glue logic. When interfacing to the 8051, the SCLK must be
inverted. The Microprocessor Interfacing section explains how
to interface to some popular DSPs and microcontrollers. Figure
4, Figure 5, and Figure 6 show the timing diagram for a serial
read and write to the AD5532. The serial interface works with
both a continuous and a noncontinuous serial clock. The first
falling edge of
SYNC
resets a counter that counts the number of
serial clocks to ensure the correct number of bits are shifted in
and out of the serial shift registers. Any further edges on
SYNC
are ignored until the correct number of bits are shifted in or
out. Once the correct number of bits for the selected mode has
been shifted in or out, the SCLK is ignored. In order for another
serial transfer to take place the counter must be reset by the
falling edge of
SYNC
.
In readback, the first rising SCLK edge after the falling edge of
SYNC
causes D
OUT
to leave its high impedance state and data is
clocked out onto the D
OUT
line and also on subsequent SCLK
rising edges. The D
OUT
pin goes back into a high impedance
state on the falling edge of the 14th SCLK. Data on the D
IN
line
is latched in on the first SCLK falling edge after the falling edge
of the
SYNC
signal and on subsequent SCLK falling edges.
During read-back D
IN
is ignored. The serial interface does
not shift data in or out until it receives the falling edge of the
SYNC
signal.
Table 10
Pin Description
SER/PAR This pin is tied high to enable the serial interface
and to disable the parallel interface. The serial
interface is controlled by the four pins that follow.
SYNC,
D
IN
, SCLK
Standard 3-wire interface pins. The SYNC pin is
shared with the CS function of the parallel interface.
D
OUT
Data Out pin for reading back the contents of the
DAC registers. The data is clocked out on the rising
edge of SCLK and is valid on the falling edge of
SCLK.
Mode
Bits
The four different modes of operation are described
in the Modes of Operation section.
Cal Bit
In DAC mode, this is a test bit. When high, it loads all
0s or all 1s to the 32 DACs simultaneously. In ISHA
mode, all 32 channels acquire V
IN
at the same time
when this bit is high. In ISHA mode, the acquisition
time is then 45 μs (typ) and accuracy may be
reduced. This bit is set low for normal use.
Offset Sel
Bit
If this is set high, the offset channel is selected and
Bits A4–A0 are ignored.
Test Bit Must be set low for correct operation of the part.
A4–A0
Used to address any one of the 32 channels
(A4 = MSB of address, A0 = LSB).
DB13–
DB0
Used to write a 14-bit word into the addressed DAC
register. Only valid when in DAC mode.
00939-C-020
OFFSET_SEL A4–A0
CAL00
MSB LSB
MODE BIT 1 MODE BIT 2
MODE BITS
0
TEST BIT
OFFSET_SEL
A4–A0
CAL10
MSB LSB
MODE BITS
DB13–DB0
0
TEST BIT
a. 10-BIT SERIAL WRITE WORD (ISHA MODE)
b. 24-BIT INPUT SERIAL WRITE WORD (DAC MODE)
c. INPUT SERIAL INTERFACE (ACQUIRE AND READ-BACK MODE)
d. INPUT SERIAL INTERFACE (READ-BACK MODE)
OFFSET_SEL A4–A0CAL01
MSB LSB
MODE BITS
DB13–DB00
TEST BIT
10-BIT
SERIAL WORD
WRITTEN TO PART
14-BIT DATA
READ FROM PART AFTER
NEXT FALLING EDGE OF SYNC
(DB13 = MSB OF DAC WORD)
MSBLSB
10-BIT
SERIAL WORD
WRITTEN TO PART
14-BIT DATA
READ FROM PART AFTER
NEXT FALLING EDGE OF SYNC
(DB13 = MSB OF DAC WORD)
OFFSET_SEL
A4–A0CAL11
MSB LSB
MODE BITS
DB13–DB00
TEST BIT
MSBLSB
Figure 21. Serial Interface Formats