Datasheet

AD5530/AD5531
Rev. B | Page 5 of 20
AC PERFORMANCE CHARACTERISTICS
V
DD
= 10.8 V to 16.5 V, V
SS
= −10.8 V to −16.5 V; GND = 0 V; R
L
= 5 kΩ and C
L
= 220 pF to GND. All specifications T
MIN
to T
MAX
, unless
otherwise noted.
Table 3.
Parameter B Version Unit Test Conditions/Comments
DYNAMIC PERFORMANCE
Output Voltage Settling Time 20 μs typ
Full-scale change to ±½ LSB. DAC latch contents alternately
loaded with all 0s and all 1s.
Slew Rate 1.3 V/μs typ
Digital-to-Analog Glitch Impulse 120 nV-s typ
DAC latch alternately loaded with 0x0FFF and 0x1000. Not
dependent on load conditions.
Digital Feedthrough 0.5 nV-s typ Effect of input bus activity on DAC output under test.
Output Noise Spectral Density @ 1 kHz 100 nV/√Hz typ All 1s loaded to DAC.
STANDALONE TIMING CHARACTERISTICS
V
DD
= 10.8 V to 16.5 V, V
SS
= −10.8 V to −16.5 V; GND = 0 V; R
L
= 5 kΩ and C
L
= 220 pF to GND. All specifications T
MIN
to T
MAX
, unless
otherwise noted.
Table 4.
Parameter Limit at T
MIN
, T
MAX
Unit Description
1, 2
f
MAX
7 MHz max SCLK frequency
t
1
140 ns min SCLK cycle time
t
2
60 ns min SCLK low time
t
3
60 ns min SCLK high time
t
4
50 ns min
SYNC to SCLK falling edge setup time
t
5
40 ns min
SCLK falling edge to
SYNC rising edge
t
6
50 ns min
Min
SYNC high time
t
7
40 ns min Data setup time
t
8
15 ns min Data hold time
t
9
5 ns min
SYNC high to LDAC low
t
10
50 ns min
LDAC pulse width
t
11
5 ns min
LDAC high to SYNC low
t
12
50 ns min
CLR
pulse width
1
Guaranteed by design, not subject to production test.
2
Sample tested during initial release and after any redesign or process change that can affect this parameter. All input signals are measured with t
R
= t
F
= 5 ns (10% to
90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
SCLK
SYNC
SDIN
MSB
DB15 DB14 DB11 DB0
LSB
t
1
t
3
t
2
t
5
t
4
t
6
t
7
t
8
t
9
t
10
t
11
t
12
LDAC
1
CLR
1
LDAC CAN BE TIED PERMANENTLY LOW, IF REQUIRED.
0
0938-002
Figure 2. Timing Diagram for Standalone Mode