Datasheet

REV. B–4–
AD5516
TIMING DIAGRAMS
t
12
SCLK
SYNC
DIN
BUSY
RESET
12 1718
t
3
t
7
t
4
t
5
t
2
t
1
t
6
t
9
MODE2
t
8
MODE1
BIT 17 BIT 0
LSBMSB
Figure 1. Serial Interface Timing Diagram
SCLK
SYNC
D
IN
D
OUT
BUSY
BIT 17 BIT 0 BIT 17 BIT 0
INPUT WORD FOR DEVICE N+1
UNDEFINED INPUT WORD FOR DEVICE N
INPUT WORD FOR DEVICE N
BIT 17 BIT 0
t
7
MODE2
t
3
t
2
t
1
t
6
t
10
t
5
t
4
t
11
t
8
MODE1
LSBMSB
Figure 2. Daisy-Chaining Timing Diagram
TO OUTPUT
PIN
C
L
50pF
200␮A
I
OH
200␮A
I
OL
1.6V
Figure 3. Load Circuit for D
OUT
Timing Specifications