Datasheet

REV. B
AD5516
–3–
AC CHARACTERISTICS
(V
DD
= +4.75 V to +13.2 V, V
SS
= –4.75 V to –13.2 V; AV
CC
= 4.75 V to 5.25 V; DV
CC
= 2.7 V to 5.25 V;
AGND = DGND = DACGND = 0 V; REF IN = 3 V. All outputs unloaded.
All specifications T
MIN
to T
MAX
, unless otherwise noted.)
Parameter
1, 2
A Version
3
Unit Conditions/Comments
Output Voltage Settling Time (Mode 1)
4
100 pF, 5 kW Load Full-Scale Change
AD5516–1 32 ␮s max
AD5516–2 32 ␮s max
AD5516–3 36 ␮s max
Output Voltage Settling Time (Mode 2)
4
100 pF, 5 kW Load, 127 Code Increment
AD5516–1 2.5 ␮s max
AD5516–2 3.35 ␮s max
AD5516–3 7 ␮s max
Slew Rate 0.85 V/␮s typ
Digital-to-Analog Glitch Impulse 1 nV-s typ 1 LSB Change around Major Carry
Digital Crosstalk 5 nV-s typ
Analog Crosstalk
AD5516–1 1 nV-s typ
AD5516–2 5 nV-s typ
AD5516–3 20 nV-s typ
Digital Feedthrough 1 nV-s typ
Output Noise Spectral Density @ 10 kHz
AD5516–1 150 nV/(Hz)
1/2
typ
AD5516–2 350 nV/(Hz)
1/2
typ
AD5516–3 700 nV/(Hz)
1/2
typ
NOTES
1
See Terminology section.
2
Guaranteed by design and characterization; not production tested.
3
A version: Industrial temperature range –40∞C to +85∞C.
4
Timed from the end of a write sequence and includes BUSY low time.
Specifications subject to change without notice.
Limit at T
MIN
, T
MAX
Parameter
1, 2, 3
(A Version) Unit Conditions/Comments
f
UPDATE1
32 kHz max DAC Update Rate (Mode 1)
f
UPDATE2
750 kHz max DAC Update Rate (Mode 2)
f
CLKIN
20 MHz max SCLK Frequency
t
1
20 ns min SCLK High Pulsewidth
t
2
20 ns min SCLK Low Pulsewidth
t
3
15 ns min SYNC Falling Edge to SCLK Falling Edge Setup Time
t
4
5 ns min D
IN
Setup Time
t
5
5 ns min D
IN
Hold Time
t
6
0 ns min SCLK Falling Edge to SYNC Rising Edge
t
7
10 ns min Minimum SYNC High Time (Standalone Mode)
t
7MODE2
400 ns min Minimum SYNC High Time (Daisy-Chain Mode)
t
8MODE1
10 ns min BUSY Rising Edge to SYNC Falling Edge
t
9MODE2
200 ns min 18th SCLK Falling Edge to SYNC Falling Edge (Standalone Mode)
t
10
10 ns min SYNC Rising Edge to SCLK Rising Edge (Daisy-Chain Mode)
t
11
4
20 ns max SCLK Rising Edge to D
OUT
Valid (Daisy-Chain Mode)
t
12
20 ns min RESET Pulsewidth
NOTES
1
See Timing Diagrams in Figures 1 and 2.
2
Guaranteed by design and characterization; not production tested.
3
All input signals are specified with tr = tf = 5 ns (10% to 90% of DV
CC
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
4
This is measured with the load circuit of Figure 3.
Specifications subject to change without notice.
TIMING CHARACTERISTICS
(V
DD
= +4.75 V to +13.2 V, V
SS
= – 4.75 V to –13.2 V; AV
CC
= 4.75 V to 5.25 V; DV
CC
= 2.7 V to 5.25 V;
AGND = DGND = DACGND = 0 V. All specifications T
MIN
to T
MAX
, unless otherwise noted.)